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Note 40.0 FPJ11 Theory of Operation No replies
FURILO::JACKSON "If you've got straight trousers, " 236 lines 13-FEB-1986 00:26
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| d i g i t a l | | uNOTE # 040 |
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+----------------------------------------------------+-----------------+
| Title: FPJ11 Theory of Operation | Date: 17-SEP-85 |
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| Originator: Bill Jackson | Page 1 of 4 |
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The goal of this MicroNote is to introduce the FPJ11, a floating point
coprocessor to the DCJ11, and to explain the interprocessor
communication between the FPJ11 and DCJ11. Figure 1 shows a typical
DCJ11 based system which includes the FPJ11. For a discussion of FPJ11
support on the KDJ11-A processor, see MicroNote #025.
+-------+ +------+
| | | |
| DCJ11 | | |
| |----------------------------------------------------| |
| | DATA BUS | |
| |----+ +--------------+ +--------------+ +---------| |
| | | | | | | | | |
| | | | +-DMR | | | | | |
| | | | | +--+--+---+ +-+--+--+ | |
| | | | V | FPJ11 | | | | BUS |
| | | | +-----+ | | | CACHE | |INTER-|
| DMR |<---+ +--| SI +--+ ACK | | | | FACE |
| | | | | +--+ STL | | | | |
| | | | | | | DV | | | | |
| | | | +-----+ | OP | | | | |
| | | | | RDY | | | | |
| FPE |<---+-+-----------+ FPE | | | | |
| | | | | | | | | |
| AIO +----+-+---------->| AIO<3:07| | | | |
| | | | | ALE | | | | |
| +----+-+---------->| STRB | | | | |
| +----+-+---------->| PRDC | | | | |
| | | | | ABORT | | | | |
| | | | | | | | | |
| | | | +---+ |ADDR<2:0>| | | | |
+-------+ | | | L | +---+-+---+ +--+-+--+ | |
| | | A | | | | | | |
| +--+ T +--------+ +---------------+ +---------+ |
| | C | ADDRESS BUS | |
+----+ H +--------------------------------------+ |
+---+ | |
+------+
Typical DCJ11/FPJ11 Application
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The FPJ11 is a single chip floating point accelerator for the DCJ11
microprocessor. Its coprocessor interface, along with optimizations
within the chip allow for 5 to 8 times acceleration over the DCJ11
microcoded floating point performance. The FPJ11 provides
o Complete FP11 floating point instructions (46)
o Two FP11 floating point data types (F and D)
o Six 64-bit floating point accumulators
o FEC floating exception code register
The FPJ11 interfaces as a true Co-processor. The Bus Interface Unit or
BIU) inputs all instruction stream data and decodes instructions in
parallel with the DCJ11. Support microcode in the DCJ11 initiates all
I/O cycles required by the FPJ11. This Co-processor interface allows
overlap of floating point instruction executing in the FPJ11 and integer
instructions executing in the DCJ11. This allows for reduced execution
time by interleaving floating point and integer instructions.
The interface to the FPJ11 involves several DCJ11 signals which indicate
the state of the DCJ11 processor, and synchronize the two processors.
Table 1 lists the signals and their use in the FPJ11 interface, Figure 1
shows their use.
TABLE 1
DCJ11/FPJ11 signals
DCJ11 signal Use
AIO<3:0> Indicate to FPJ11 current DCJ11 cycle type
PRDC signal instruction decode to FPJ11
STRB signal beginning of bus cycle to FPJ11
DMR used by FPJ11 to stall the DCJ11
FPE indicate to DCJ11 a floating point exception
ALE used to latch cache hit data (trailing edge)
DV used to latch non-cache data (trailing edge)
DAL<2:0> indicate GPREAD and GPWRITE information
FPA-OP signal to SI that writes come from FPA
FPA-STL used to stall DCJ11 during multiple FPA
instructions
FPA-RDY indicates FPA data will be ready in 125ns
FPA-ACK enable FPA output drivers
The DCJ11 supports several types of bus operations in communicating with
the external system. Since the FPJ11 relies on the DCJ11 to initiate
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all I/O cycles, the FPJ11 will monitor DCJ11 I/O cycles for activity.
When specific I/O cycles occur, the FPJ11 will 'wake up' and start
processing. A subset of the DCJ11 bus cycles are used by the FPJ11 in
communicating with the DCJ11 and the system interface (SI). These bus
cycles are listed in Table 2. The bus read and write cycles are used to
read/write data to/from memory (or cache). The GP transactions are used
for interprocessor communications between the DCJ11 and FPJ11.
Table Y
DCJ11 bus operations
Cycle Description
IREAD latched to search for FP instruction
DREAD used for data fetches for FP instructions
WRITE used to write FP data back to memory
GPREAD used to read FP data to DCJ11 internal registers
GPWRITE used to write FP data to DCJ11 internal
registers
The DCJ11 divides all bus reads into 3 categories: Instruction stream
Demand READ (IDREAD), Instruction stream Request READ (IRREAD), and Data
stream READ (DREAD). Instruction stream reads are used by the DCJ11 to
fetch instruction stream data such as PDP-11 instructions, immediate
data and absolute data. All other DCJ11 reads are classified as Data
stream reads (for more information on DCJ11 bus cycles and data
classification see the DCJ11 data sheet EK-26921-00)
Request reads are reads that the DCJ11 will attempt when doing internal
cycles such as register transfers. This is an attempt at filling the
DCJ11 4 stage pipeline. Demand reads are reads that must be completed
in order to finish an instruction. The DCJ11 will always try to keep
the pipeline full by doing request reads, but will do demand reads as
necessary.
The most typical FPJ11 operation is the common FP11 instruction that
reads some data from memory, operates on it, then writes the result back
to memory. In this operation, the FPJ11 monitors the DCJ11 bus cycles
for either type of instruction stream read. When the FPJ11 sees any
type of Instruction stream read, it latches the data from the
data/address lines (DAL) and holds it in its instruction register. The
FPJ11 keeps doing this until it sees the DCJ11 indicate that it is now
doing a instruction decode by the assertion of the DCJ11 signal PRDC.
The FPJ11 then does a parallel decode of the instruction and checks if
it is a floating point instruction. If the instruction is not a
floating point instruction, the FPJ11 'goes to sleep' and continues to
latch all I-stream read data. If the instruction is a floating point
instruction, the DCJ11 will initiate all bus cycles while the FPJ11 will
remove data from the bus. The FPJ11 will then do the floating point
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operation. If the operation is a store type operation the DCJ11 will
initiate the bus write operation signaling to the FPJ11 to write data to
memory.
When either the source or destination of the floating point instruction
is a DCJ11 general purpose register, a GP cycle will be used to access
the DCJ11 register. Load type operations would use the GPWRITE bus
cycle to write the contents of the DCJ11 register to the FPJ11. GPREAD
operations are used to read data from the FPJ11 and deposit it into the
DCJ11 general purpose registers.
Because of the overlapping instruction capability, the DCJ11/FPJ11
combination can start to fetch operands for a next floating point
operation while one is executing. Because there is a single datapath
internal to the FPJ11, this prefetched data must not get to the
execution unit until the current operation is finished. The FPJ11 will
output FPA-STL to the DCJ11 if the current operation will not be
completed before all of the data is ready. This mechanism guarantees
that the datapath will only be used by one floating point operation at a
time. When the FPJ11 is done with the current operation the DCJ11 is
continued, and the floating point operation proceeds.
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