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Note 34.0 Programming KXT11-C Multi SLU No replies
FURILO::GIORGETTI 1413 lines 3-SEP-1985 17:17
--------------------------------------------------------------------------------
+---------------+ +-----------------+
| d i g i t a l | | uNOTE # 034 |
+---------------+ +-----------------+
+----------------------------------------------------+-----------------+
| Title: Programming the KXT11-C Multiprotocol SLU | Date: 19-Jul-85 |
+----------------------------------------------------+-----------------+
| Originator: Scott Tincher | Page 1 of 24 |
+----------------------------------------------------+-----------------+
The KXT11-CA single board computer provides a two-channel multiprotocol
serial line unit. The SLU is implemented with an NEC uPD7201 chip.
This Micronote will explain the operation of this SLU and provide
example programs which display its capabilities. The example programs
will be written in Macro-11 so it is assumed that the programmer is
familiar with Macro-11 and either the RT-11 or RSX KXT11-C Software
Toolkits. It should be noted that the DIGITAL operating system
MicroPower/Pascal provides a device handler for the uPD7201 chip.
FEATURES/CAPABILITIES
The multiprotocol SLU supplies the KXT11-C with the following features
and capabilities:
o Two full duplex channels
- Channel A provides full modem control
- Channel B provides data and timing leads only
o Each channel may be operated in one of three modes:
- Asynchronous
o 5, 6, 7, or 8 Data bits
o 1, 1-1/2, or 2 Stop bits
o Odd, Even, or No Parity
o Break generation and detection
o Interrupt on Parity, Overun, or Framing Errors
- Character-oriented synchronous
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o Monosync, Bisync, and External Sync Operations
o Software Selectable Sync Characters
o Automatic Sync Insertion
o CRC Generation and Checking
- Bit-oriented synchronous
o HDLC and SDLC Operations
o Abort Sequence Generation and Detection
o Automatic Zero Insertion and Detection
o Address Field Recognition
o CRC Generation and Checking
o I-Field Residue Handling
o Programmable Baud Rates
o Double Buffered Transmitted Data
o Quadruply Buffered Received Data
o Programmable CRC Algorithm
o Channel A may utilize the DMA controller to transfer data
REGISTER DESCRIPTION
The multiprotocol SLU is controlled by manipulating the registers of the
uPD7201 chip as well as registers in support chips that provide access
to the baud rate generator and the modem control signals. This section
will provide a brief description of the registers necessary to program
the multiprotocol SLU.
uPD7201 Registers
This section will describe the registers found in the uPD7201 itself.
These registers are found in both channels of the uPD7201 unless
otherwise indicated.
Control Register 0
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
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Bits 0,1,2: Register Pointer
These bits are used to specify which register will be
affected by the next Control Register Write or Status
Register Read. After a reset the register pointer is set
to 0. When the register pointer is set to a value other
than 0 the next control or status access is to the
specified register, then the pointer is reset to 0.
Bits 3,4,5: Command
These bits are used to select the command to be sent to
the uPD7201. A list of these commands follows:
NULL (000)
This command has no effect and is used when setting the
register pointer or issuing a CRC command.
SEND ABORT (001)
When operating in the SDLC mode, this command causes the
uPD7201 to transmit the SDLC abort code.
RESET EXTERNAL/STATUS INTERRUPTS (010)
Clears any pending external interrupts and reenables the
latches so that new interrupts may be detected.
CHANNEL RESET (011)
After issuing a reset command the receivers and
transmitters are disabled, the transmitters are set in the
marking (high) state, and the modem control outputs are
set high. In addition, all interrupts are disabled, and
all interrupt and DMA requests are cleared. All control
registers must be rewritten after a reset. One NOP
instruction must be issued before writing a new command.
ENABLE INTERRUPT ON NEXT CHARACTER (100)
When operating in Interrupt on First Character mode this
command is issued to re-enable the interrupt logic for the
next received character.
RESET PENDING TRANSMITTER INTERRUPT/DMA REQUEST (101)
Issue this command to reset a pending Transmitter Buffer
Becoming Empty interrupt or DMA request without sending
another character.
ERROR RESET (110)
This command resets a Special Receive Condition interrupt.
It also re-enables the Parity and Overrun Error latches
that allow you to check for these errors at the end of a
message.
END OF INTERRUPT (111) (Channel A only)
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When an interrupt request has been issued by the uPD7201
all lower priority interrupts are blocked to permit the
current interrupt to be serviced. At some point in the
interrupt service routine this command must be issued to
re-enable the daisy chain and permit any pending lower
priority interrupt requests to occur.
Bits 6,7: CRC Control Commands
These commands control the operation of the CRC
generator/checker logic.
NULL (00)
This command has no effect and is used when issuing other
commands or setting the register pointer.
RESET RECEIVER CRC CHECKER (01)
This command resets the CRC checker to 0 when the channel
is in a synchronous mode and resets to all ones when is
SDLC mode.
RESET TRANSMITTER CRC GENERATOR (10)
This command resets the CRC generator to 0 when the
channel is in a synchronous mode and resets to all ones
when is SDLC mode.
RESET IDLE/CRC LATCH (11)
This command resets the Idle/CRC latch so that when a
transmitter underrun condition occurs, the transmitter
enters the CRC phase of operation and begins to send the
16-bit CRC character calculated up to that point. The
latch is then set so that if the underrun conition
persists, idle characters are sent following the CRC.
After a hardware or software reset, the latch is in the
set state.
Control Register 1
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bit 0: External/Status Interrupt Enable
When this bit is set to one, the uPD7201 issues an
interrupt whenever any of the following occur:
o transition of DCD input
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o transition of CTS input
o transition of synch input
o entering or leaving synchronous Hunt Phase
break detection or termination
o SDLC abort detection or termination
o Idle/CRC latch becoming set (CRC being sent)
Bit 1: Transmitter Interrupt Enable
When this bit is set to one, the uPD7201 issues an
interrupt when:
o The character currently in the transmitter buffer is
transferred to the shift register (Transmitter Buffer
Becoming Empty)
o The transmitter enters Idle Phase and begins
transmitting sync or flag characters
Bit 2: Status Affects Vector (Channel B only)
This bit must always be programmed to one so that the
fixed vector programmed into Control Register 2B is
modified to indicate the cause of the interrupt.
Bits 3,4: Receiver Interrupt Mode
This field determines how the uPD7201 handles the
character receive conditions.
RECEIVER INTERRUPTS/DMA REQUEST DISABLED (00)
The uPD7201 does not issue an interrupt or DMA
request when a character has been received.
(Polled Mode).
INTERRUPT ON FIRST RECEIVED CHARACTER ONLY (01)
The uPD7201 issues an interrupt for the first
character received after an Enable Interrupt on
First Character Command (CR0) has been given. If
the channel is in DMA mode then a DMA request is
issued for each character received including the
first.
INTERRUPT ON ALL RECEIVED CHARACTERS (10)
An interrupt is issued whenever a character is
present in the receive buffer. A DMA request is
issued if the channel is in DMA mode. A parity
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error is considered a special receive condition.
INTERRUPT ON ALL RECEIVED CHARACTERS (11)
This mode is the same as above except that a parity
error is not treated as a special receive
condition.
The following are always considered special receive
conditions:
o Receiver Overrun Error
o Asynchronous Framing Error
o SDLC End of Message
Bits 5,6,7: These bits should always be programmed to 0.
Control Register 2 (Channel A)
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bits 0,1: DMA Mode Select
These bits determine the mode in which channels A and B
operate. If a channel operates in a non-DMA mode it my
perform transfers in either polled or interrupt mode.
Bit 1 Bit 0 Channel A Channel B
0 0 Non-DMA Non-DMA
0 1 DMA Non-DMA
1 0 Illegal Illegal
1 1 Illegal Illegal
Bit 2: Priority
This bit is used to select the appropriate internal
priorities for interrupts. The Channel A receiver always
has a higher priority than the Channel A transmitter when
Channel A is in DMA mode.
If Channels A and B are both in Interrupt Mode:
0 - RxA > TxA > RxB > TxB > extA > extB
1 - RxA > RxB > TxA > TxB > extA > extB
If Channel A is in DMA mode and Channel B is in Interrupt
Mode:
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0,1 - RxA > RxB > TxB > extA > extB
Bits 3,5,6,7: These bits must be programmed to 0.
Bit 4: This bit must always be programmed to 1.
Control Register 2 (Programmed in Channel B for both channels)
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bits 0..7: Interrupt Vector
The native firmware of the KXT11-C initializes the uPD7201
interrupt vector to 70(8). All interrupts use this
vector. In order to determine the cause of the interrupt
the uPD7201 must be operated with Condition Affects Vector
enabled. (Control Register 1 - Bit 2). When this bit is
set the vector is modified to reflect the cause of the
interrupt. This modified vector is read from Status
Register 2.
Control Register 3
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bit 0: Receiver Enable
0 - Disables the receiver
1 - Enables the receiver
Bit 1: Sync Character Load Inhibit
In a synchronous mode, this bit inhibits the transfer of
sync characters to the receiver buffer. When using the
uPD7201's CRC checking capabilities this feature should
only be used to strip leading sync characters preceding a
message since the load inhibit does not exclude sync
characters embedded in the message from the CRC
calculations. Synchronous protocols using other types of
block checking such as checksum or LRC are free to strip
embedded sync characters with this bit.
Bit 2: Address Search Mode
In SDLC mode, setting this bit places the uPD7201 in
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Address Search mode where character assembly does not
begin until the 8-bit character (secondary address field)
following the starting flag of a message matches either
the address programmed into CR6 or the global address
11111111.
Bit 3: Receiver CRC Enable
This bit enables (enable = 1) the CRC checker in COP mode
to allow the selective inclusion or exclusion of
characters form the CRC calculation.
Bit 4: Enter Hunt Phase
The uPD7201 automatically enters Hunt Phase after a reset.
Setting this bit to 1 causes the uPD7201 to re-enter the
Hunt Phase.
Bit 5: Auto Enables
Setting this bit to 1 causes the DCD and CTS inputs to act
as enable inputs to the receiver and transmitter,
respectively.
Bits 6,7: Number of Received Bits/Character
This field specifies the number of data bits per received
character:
Bit 7 Bit 6 Bits/Character
0 0 5
0 1 7
1 0 6
1 1 8
Control Register 4
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bit 0: Parity Enable
Setting this bit to 1 adds an extra data bit containing
parity information to each transmitted cahracter. Each
received character is expected to contain this extra bit
and the receiver parity checker is enabled.
Bit 1: Parity Even/Odd
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0 - Odd parity generation and checking
1 - Even parity generation and checking
Bits 2,3: Number of Stop Bits/Sync Mode
This field specifies whether the channel is used in a
synchronous mode or in asynchronous mode. In asynchronous
mode, this field also specifies the number of stop bits
used by the transmitter. The receiver always checks for
one stop bit.
Bit 3 Bit 2 Mode
0 0 Synchronous mode
0 1 Asynch Mode, 1 stop bit
1 0 Asynch Mode, 1-1/2 stop bits
1 1 Asynch Mode, 2 stop bits
Bits 4,5: Sync Mode
These bits select the synchronous protocol to use if the
channel has been programmed in a synchronous mode.
Bit 5 Bit 4 Mode
0 0 Monosync
0 1 Bisync
1 0 SDLC
1 1 External Synchronization
Bits 6,7: Clock Rate
These bits specify the relationship between the
transmitter and receiver clock inputs and the actual data
rate. When operating in synchronous mode the clock rate
must be specified as 1X the data rate.
Bit 7 Bit 6 Clock Rate
0 0 Clock Rate = 1X Data Rate
0 1 Clock Rate = 16X Data Rate
1 0 Clock Rate = 32X Data Rate
1 1 Clock Rate = 64X Data Rate
Control Register 5
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bit 0: Transmitter CRC Enable
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A 1 enables the CRC generator calculation. By setting or
resetting this bit just before loading the next character,
it and subsequent characters are included or excluded from
the calculation.
Bit 1: RTS
In synchronous and SDLC modes, setting this bit to 1
causes the RTS pin to go low while a 0 causes it to go
high. In asynchronous mode, setting this bit to 0 does
not cause RTS to go high until the transmitter is
completely empty.
Bit 2: CRC Polynomial Select
A 0 selects the CRC-CCITT Polynomial (X**16 + X**12 + X**5
+ 1). A 1 selects the CRC-16 Polynomial (X**16 + X**15 +
X**2 +1). The CRC-CCITT polynomial must be selected when
in SDLC mode.
Bit 3: Transmitter Enable
After a reset the transmitted data output is held high
(marking) and the transmitter is disabled until this bit
is set.
Bit 4: Send Break
Setting this bit to 1 forces the transmitter output low
(spacing).
Bits 5,6: Transmitted Bits/Character
These bits specify the number of data bits per transmitted
character.
Bit 6 Bit 5 Bits/Character
0 0 5 (or less)
0 1 7
1 0 6
1 1 8
Bit 7: DTR
When this bit is 1, the DTR output is active.
Control Register 6
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
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Bits 0..7: Sync Byte 1
Sync byte 1 is used in the following modes:
Monosync: The 8-bit character transmitted during
the Idle Phase.
Bisync: The least significant 8 bits of the 16-bit
transmit and receive sync character.
External Sync: Sync character transmitted during
the Idle Phase.
SDLC: Secondary address value matched to the
Secondary Address field of the
SDLC frame when the uPD7201 is in Address
Search Mode.
Control Register 7
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bits 0..7: Sync Byte 2
Sync Byte 2 is used in the following modes:
Monosync: 8-bit sync character matched by the receiver.
Bisync: Most significant 8 bits of the 16-bit transmit
and receive sync characters.
SDLC: Must contain the flag value, 01111110, for flag
matching by the uPD7201 receiver.
Status Register 0
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bit 0: Received Character Available
When this bit is set, it indicates that one or more
characters are available in the receiver buffer. Once all
of the available characters have been read, the uPD7201
resets this bit until a new character is received. By
utilizing this bit the programmer my run at higher data
rates than normal because it will be possible to capture
more that one character per interrupt service routine.
Bit 1: Interrupt Pending (Channel A only)
The interrupt pending bit is used with the interrupt
vector register (status register 2) to make it easier to
determine the uPD7201's interrupt status. In Non-vectored
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Interrupt mode, interrupt pending is set when status
register 2B is read. If status affects vector is enabled
and interrupt pending is set, the vector read from SR2
contains valid condition information.
Bit 2: Transmitter Buffer Empty
This bit is set whenever the transmitter buffer is empty,
except during the transmission of the CRC. After a reset,
the buffer is considered empty and transmitter buffer
empty is set.
Bit 3: DCD (Data Carrier Detect)
This bit reflects the inverted state of the DCD input.
When DCD is low, the DCD status bit is high. Any
transition of this bit causes an External/Status Interrupt
request.
Bit 4: Sync Status
The bit assumes different meanings depending on the
operating mode of the uPD7201.
Asynch mode: Sync Status reflects the inverted state fo
the Sync input. Any transition of this bit causes an
External/Status interrupt request.
External Sync mode: Sync Status operates in the same
manner as asynch mode. A low-to-high transition indicates
that synchronization has been achieved and character
assembly begins.
Monosync, Bisync, SDLC modes: Sync Status indicates
whether the receiver is in the Sync Hunt (bit =1) or the
Receive Data Phase (bit = 0) of operation.
Bit 5: CTS (Clear to Send)
This bit reflects the inverted state of the CTS input.
Any transition of this bit causes an External/Status
interrupt request.
Bit 6: Idle/CRC
This bit indicates the state of the Idle/CRC latch used in
synchronous and SDLC modes.
Bit 7: Break/Abort
In async mode, this bit indicates that the detection of a
break sequence that occurs when the input is held low
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(spacing) for more than one character time. This bit is
reset when the input returns high (marking).
In SDLC mode, Break/Abort indicates the detection of an
abort sequence when 7 or more ones are received in
sequence.
Any transition of the Break/Abort bit causes an
External/Status interrupt.
Status Register 1
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bit 0: All Sent
In async mode, this bit is set when the transmitter is
empty and reset when a character is present in the
transmitter buffer or shift register. In synchronous and
SDLC modes, this bit is always 1.
Bits 1,2,3: SDLC Residue Code
The data portion of an SDLC message can consist of any
number of bits and not necessarily an integral number of
characters. Special logic determines and reports when the
End of Frame flag has been received, the boundary between
the data field, and the CRC character in the last few data
characters that were read.
Bit 4: Parity Error
This bit is set when parity is enabled and the received
parity bit does not match the sense calculated from the
data bits.
Bit 5: Receiver Overrun Error
This error occurs when the receiver buffer already
contains three characters and a fourth character is
completely received, overwriting the last character in the
buffer.
Bit 6: CRC/Framing Error
In Async modem a framing error is flagged when no sop bit
is detected at the end of a character.
In sync and SDLC modes, this bit indicates the result of
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the comparison between the current CRC result and the
appropriate check value.
Bit 7: End of SDLC Frame
This flag is used in SDLC mode to indicate that the End of
FRame flag has been received and that the CRC error flag
and residue code is valid.
Status Register 2
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bits 0..7: Interrupt Vector (Channel B only)
Reading Status Register 2B returns the interrupt vector
that was programmed into Control Register 2B. If
Condition Affects Vector is enabled the value of the
vector is modified as follows:
Condition Affects Vector Modifications
Bit 2 Bit 1 Bit 0 Condition
1 1 1 No interrupt pending
0 0 0 Channel B Transmitter Buffer Empty
0 0 1 Channel B External/Status Change
0 1 0 Channel B Received Character Available
0 1 1 Channel B Special Receive Condition
1 0 0 Channel A Transmitter Buffer Empty
1 0 1 Channel A External/Status Change
1 1 0 Channel A Received Character Available
1 1 1 Channel A Special Receive Condition
- Table 1 -
Code 111 has two meanings: either Channel A Special
Receive Condition or no interrupt pending. In order to
distinguish between the two, the Interrupt Pending bit
(SR0) must be examined.
Baud Rate Generator Registers
Programmable baud rates for channels A and B are supplied by an
Intel 8254-2 timing controller chip with two counters operating
at 9.8304 MHz. A third counter that operates at 800 Hz is
available for general use. This general purpose counter issues a
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level 6 interrupt request to the T-11 via vector 104.
Programming these counters is straightforward. First, a Timer
Control register is initialized to provide the proper counting
mode. Then a divider ratio is loaded into a Timer Data register
to obtain the desired baud rate. The divider ratio is obtained
from the following calculations:
For synchronous transmission,
Synchronous bit rate = 9830.4K / divider ratio
Therefore,
divider ratio = 9830.4K / synchronous bit rate
A few examples,
Bit Rate Ratio
1200 8192
9600 1024
38.4K 256
76.8K 128
For asynchronous transmission (assuming that the clock rate is
divided by 16),
Asynchronous bit rate = 9830.4K (1/16) / divider ratio
Therefore,
divider ratio = 614.4K / asynchronous bit rate
A few examples,
Bit Rate Ratio
1200 512
9600 64
38.4K 16
76.8K 8
Timer Control Register
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bit 0: BCD or Binary
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0 - Use 16-bit binary counter
1 - Use BCD counter with four decades
Bits 1,2,3: Mode Select
The mode of the counter is selected with these bits:
Bit 3 Bit 2 Bit 1 Mode
0 0 0 Interrupt on Terminal Count
0 0 1 Not supported
0 1 0 Rate Generator
0 1 1 Square Wave Generator
1 0 0 Software Triggered Strobe
1 0 1 Not supported
1 1 0 Reserved
1 1 1 Reserved
Bits 4,5: Read/Write Sequence Selection
The Timer Data registers are programmed on a byte basis.
These bits determine the sequence in which the Timer Data
registers interpret the data.
Bit 5 Bit 4 Sequence
0 0 Counter Latch Command
0 1 Read/Write least significant byte only
1 0 Read/Write most significant byte only
1 1 Read/Write least significant byte first,
then most significant byte
Bits 6,7: Counter Select
These bits select which counter is being programmed.
Bit 7 Bit 6 Counter
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Read-back command
KXT Control/Status Register A
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
This register contains some of the control lines for the uPD7201.
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Bit 0: SYNCM B
0 - Channel B receives its clock from the onboard baud
rate generator
1 - Channel B receives its clock from an external source
Bit 1: SLU2B R EN
0 - Party line receive data enabled (Board must be
properly configured)
1 - Party line receive data disabled
Bit 2: SYNCM A
0 - Channel A receives its clock from the onboard baud
rate generator
1 - Channel A receives its clock from an external source
Bit 3: Data Terminal Ready (DTR)
0 - DTR is not asserted
1 - DTR is asserted
Bit 4: Terminal in Service (Busy)
0 - Terminal in Service is not asserted
1 - Terminal in Service is asserted
Bit 5: Diagnostic Prom Enable
This bit allows two different 1K portions of the onboard
firmware to be visible at addresses 160000-163777.
Bit 6: Real Time Clock Enable
0 - The RTC interrupt is inhibited
1 - The RTC interrupt is enabled
Bit 7: Counter 2 Interrupt Enable
0 - Counter 2 interrupts are inhibited
1 - Counter 2 interrupts are enabled
The following table lists the registers that have been described
and their addresses:
KXT Control/Status Register A 177520 Read/Write
Timer Control Register 175736 Write only
Timer 2 Data Register 175734 Write only
Timer 1 Data Register 175732 Write only
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Timer 0 Data Register 175730 Write only
Timer 2 Data Register 175724 Read only
Timer 1 Data Register 175722 Read only
Timer 0 Data Register 175720 Read only
Channel B Transmitter 175716 Write only
Channel B Control Register 175714 Write only
Channel B Receiver 175712 Read only
Channel B Status Register 175710 Read only
Channel A Transmitter 175706 Write only
Channel A Control Register 175704 Write only
Channel A Receiver 175702 Read only
Channel A Status Register 175700 Read only
- Table 2 -
PROGRAMMING EXAMPLES
The following programs provide 'skeletons' on which to base user
application programs.
.TITLE SLU1.MAC
; This program utilizes the uPD7201 to transfer serial data. The
; data will be transfered out of Channel A and received by Channel
; A so a loopback connector is required (Part #H3022 or 54-16229-01).
; This example transfers the data in asynchronous mode using
; interrupts.
;
; After this program has been assembled and linked on the
; development machine use the KUI utility of the KXT11-C Software
; Toolkit to load the program into the KXT11-C to execute as
; shown in this example:
;
; SET 2
; LOAD SLU1.SAV
; EXECUTE
; !ODT
; !
; !001206
; !001302/041101
; !001304/042103
; !001306/043105
; !001310/044107
; !001312/041101
; !001314/042103
; !001316/043105
; !001320/044107
; !001322/000000
; !R4/000000
; !
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; EXIT
;
; This verifies that the data was successfully transfered. 1302 is
; the address of the transmit buffer and 1312 is the address of the
; receive buffer. R4=0 verifies that no external or special
; condition interrupts were received.
;
; Register Definitions
STATA == 175700 ; Channel A status register
RBUFA == 175702 ; Channel A receiver
CNTRLA == 175704 ; Channel A Control register
TBUFA == 175706 ; Channel A transmitter
STATB == 175710 ; Channel B status register
CNTRLB == 175714 ; Channel B control register
TIMREG == 175736 ; Timer control register
TIMER0 == 175730 ; Timer 0 data register
START::
; This section initializes the KXT11-C system environment
MTPS #340 ; Disable recognition of interrupts
MOV #ISR,@#70 ; SLU2 interrupts at location 70
MOV #340,@#72 ; Let the ISR run at priority 7
CLR R0 ; This is the transmit char counter
MOV #TBUF,R2 ; R2 points to the transmit buffer
MOV #RBUF,R3 ; R3 points to the receive buffer
CLR R4 ; This counter keeps track of external
; status changes and special receive
; receive conditions
; This section initializes the bit rate generator
MOVB #26,TIMREG ; Select timer 0, low byte only,
; mode 3, binary
MOVB #64.,TIMER0 ; This divider selects 9600 bps
; This section initializes the 7201 for asynch operation
MOVB #30,CNTRLA ; Reset Channel A
NOP ; Wait for reset to complete
MOVB #30,CNTRLB ; Reset Channel B
NOP ; Wait for reset to complete
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MOVB #2,CNTRLA ; Point to CR2A
MOVB #24,CNTRLA ; Setup bus interface options:
; No DMA, RxA>RxB>TxA..., Non-Vectored
MOVB #4,CNTRLA ; Point to CR4
MOVB #104,CNTRLA ; Set operation mode:
; No parity, asynch mode, 1 stop bit,
; clock rate = 16x data rate
MOVB #3,CNTRLA ; Point to CR3
MOVB #301,CNTRLA ; Enable receiver, char length = 8
MOVB #5,CNTRLA ; Point to CR5
MOVB #152,CNTRLA ; Enable transmitter, Char length = 8
CLRB CNTRLA ; Point to CR0
MOVB #20,CNTRLA ; Reset External/Status Interrupts
MOVB #1,CNTRLA ; Point to CR1
MOVB #36,CNTRLA ; Transmit IE, Interrupt on all
; received chars, enable condition
; affects vector
MAIN::
MTPS #0 ; Enable recognition of interrupts
MOVB (R2)+,TBUFA ; Send first character
BR . ; Stay here while the interrupts occur
ISR::
MOVB #2,CNTRLB ; Point to SR2B
MOVB STATB,-(SP) ; Store the condition affects vector
; on the stack
; This section inspects the condition affects vector to
; determine the cause of the interrupt
ROR (SP) ; Rotate bit 0 into the carry bit
BCS EXT ; If this bit was set then the
; interrupt was caused by a special
; receive condition or an external/
; status change
ROR (SP) ; Rotate bit 1 into the carry bit
BCS RCV ; If this bit was set then the
; interrupt was caused by a received
; character
;+
; If neither of the above conditions was
; satisfied then the interrupt must have
; been caused by the transmitter buffer
; going empty
;-
XMIT::
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INC R0 ; Increment the xmit char counter
CMP R0,#8. ; IF this is the eight char
BEQ 1$ ; THEN branch to 1$
MOVB (R2)+,TBUFA ; ELSE send another char
BR IDONE ; and return
1$: MOVB #50,CNTRLA ; reset pending xmit interrupt
BR IDONE ; request - then return
RCV:: MOVB RBUFA,(R3)+ ; Store this character
BR IDONE ; and return
EXT:: ; This program does not take any special action if an
; External/Status interrupt or Special Receive Condition
; occurs. Just note that it occurred (there shouldn't be
; any) and continue.
INC R4 ; Increment the counter
; and return
IDONE:: TST (SP)+ ; Fix the stack
MOVB #70,CNTRLA ; Issue end of interrupt command
RTI ; and return to main program
TBUF:: .BYTE 101,102,103,104,105,106,107,110
RBUF:: .BLKB 8.
.END START
.TITLE SLU2.MAC
; This example program for the uPD7201 transfers serial data via
; a loopback connector (part #H3022 or 54-16229) between Channel
; A's transmit and receive using the DMA controller. No ISR is
; included in this example as it is meant to show how the uPD7201
; and the DTC may work together. A 'real-life' program should
; include an ISR which monitors any External or Special Receive
; condition interrupts. For more information regarding the
; programming of the DTC please refer to MicroNote #018.
;
; After this program has been assembled and linked on the
; development machine use the KUI utility of the KXT11-C Software
; Toolkit to load the program into the KXT11-C to execute as
; shown in this example:
;
; SET 2
; LOAD SLU2.SAV
; EXECUTE
; !ODT
; !
; !001234
323
uNOTE # 034
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; !1276/041101
; !001300/042103
; !001302/043105
; !001304/044107
; !001306/041101
; !001310/042103
; !001312/043105
; !001314/044107
; !001316/000000
; !
; EXIT
;
; This verifies that the data was tranfered successfully. The
; transmit buffer begins at address 1276 and the receive buffer
; begins at address 1306.
;
; Register Assignments
MMREG == 174470 ; Master Mode Register
CMDREG == 174454 ; Command Register
CASTF0 == 174446 ; Chan 0 Chain Address Seg/Tag Field
CAOF0 == 174442 ; Chan 0 Chain Address Offset Field
CASTF1 == 174444 ; Chan 1 Chain Address Seg/Tag Field
CAOF1 == 174440 ; Chan 1 Chain Address Offset Field
STATA == 175700 ; Channel A status register
RBUFA == 175702 ; Channel A receiver
CNTRLA == 175704 ; Channel A Control register
TBUFA == 175706 ; Channel A transmitter
STATB == 175710 ; Channel B status register
CNTRLB == 175714 ; Channel B control register
TIMREG == 175736 ; Timer Control register
TIMER0 == 175730 ; Timer 0 Data register
START::
; This section initializes the KXT11-C system environment
MTPS #340 ; Disable recognition of interrupts
MOV #TBUF,R2 ; R2 points to the transmit buffer
MOV #RBUF,R3 ; R3 points to the receive buffer
; This section initializes the bit rate generator
MOVB #26,TIMREG ; Select timer 0, low byte only,
; mode 3, binary
MOVB #64.,TIMER0 ; This divider selects 9600 bps
; This section initializes the 7201 for asynch operation
324
uNOTE # 034
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MOVB #30,CNTRLA ; Reset Channel A
NOP ; Wait for reset to complete
MOVB #30,CNTRLB ; Reset Channel B
NOP ; Wait for reset to complete
MOVB #2,CNTRLA ; Point to CR2A
MOVB #25,CNTRLA ; Setup bus interface options:
; Chan A DMA, RxA>RxB>TxA...,
; Non-Vectored
MOVB #4,CNTRLA ; Point to CR4
MOVB #104,CNTRLA ; Set operation mode:
; No parity, asynch mode, 1 stop bit,
; clock rate = 16x data rate
MOVB #3,CNTRLA ; Point to CR3
MOVB #301,CNTRLA ; Enable receiver, char length = 8
;
MOVB #5,CNTRLA ; Point to CR5
MOVB #152,CNTRLA ; Enable transmitter, Char length = 8
;
CLRB CNTRLA ; Point to CR0
MOVB #20,CNTRLA ; Reset External/Status Interrupts
;
MOVB #1,CNTRLA ; Point to CR1
MOVB #16,CNTRLA ; Transmit IE, Interrupt on 1st
; received char and issue DMA request
; enable condition affects vector
; This section initializes the DMA controller
CLRB CMDREG ; Reset the DTC
MOV #0,CASTF0 ; Load Chain Address Register Seg/Tag
MOV #LOAD0,CAOF0 ; Load Chain Address Register Offset
MOV #0,CASTF1 ; Load Chain Address Register Seg/Tag
MOV #LOAD1,CAOF1 ; Load Chain Address Register Offset
MOVB #115,MMREG ; Load Master Mode Reg to Enable DTC
MOVB #240,CMDREG ; Start Chain Channel 0
MOVB #241,CMDREG ; Start Chain Channel 1
MAIN::
BR . ; Stay here while the DMA transfers
; occur
; Chain Load Region
LOAD1: .WORD 001602 ; Reload Word
