================================================================================
Note 32.0 KXT11-C Parallel I/O Prog No replies
FURILO::GIORGETTI 2476 lines 21-AUG-1985 23:19
--------------------------------------------------------------------------------
+---------------+ +-----------------+
| d i g i t a l | | uNOTE # 032 |
+---------------+ +-----------------+
+----------------------------------------------------+-----------------+
| Title: KXT11-C Parallel I/O Programming | Date: 28-JUN-85 |
+----------------------------------------------------+-----------------+
| Originator: Scott Tincher | Page 1 of 42 |
+----------------------------------------------------+-----------------+
The KXT11-CA is a single board computer that provides the user with
flexible I/O programming options. One of the onboard programmable
devices is a 20 line parallel I/O port (PIO). This note will describe
the operation of the PIO and will provide some programming examples.
Since the DIGITAL operating system MicroPower/Pascal provides a device
handler for the PIO, the programming examples included in this note will
be written in MACRO-11 for the user who wishes to program the PIO in
MACRO-11. The example programs assume the user is familiar with the
KXT11-C Software Toolkit for RT-11 or RSX.
FEATURES/CAPABILITIES
The PIO of the KXT11-C supplies the following features:
o Two 8-bit, double buffered, bidirectional I/O ports
o A 4-bit special purpose I/O port
o Four handshake modes
o REQUEST signal for utilizing the DMA controller
o Pattern recognition logic
o Three independent 16-bit counter/timers
The two 8-bit ports (A and B) are identical except that Port B can
provide external access to Counter/Timers 1 and 2. Each port may be
configured under program control as a single or double buffered port
with handshake logic or as a bit port for control applications. Pattern
recognition logic is also included in each port. This logic allows
interrupt generation whenever a specific pattern is recognized. Ports A
and B may be linked to form a 16-bit port with handshake.
When Port A or B is used as a port with handshake the control lines are
supplied by a special 4-bit port (Port C). If no handshake lines are
required then Port C may be used as a bit port. Port C also provides
external access to Counter/Timer 3 and a REQUEST line that allows the
247
uNOTE # 032
Page 2 of 42
PIO to utilize the DMA controller when transfering data.
The PIO supplies three identical 16-bit Counter/Timers. These
Counter/Timers operate at a frequency of 2 MHz which provides a
resolution of 500 ns. Each Counter/Timer may operate with one of three
output duty cycles: pulse, one-shot, or square-wave. In addition, each
unit may operate as retriggerable or non-retriggerable.
REGISTER DESCRIPTION
The following section provides a brief description of the registers of
the PIO.
MASTER CONTROL REGISTERS
There are two registers that control the overall function of the PIO,
the Master Interrupt Control Register and the Master Configuration
Control Register.
Master Interrupt Control Register
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Address = 177000
Bit 7: Master Interrupt Enable (MIE)
0 - Inhibits this device from requesting an interrupt or
responding to an interrupt acknowledge.
1 - Allows interrupt logic to operate normally.
Bits 6,5,4,3,2,1: These bits must be programmed to zero.
Bit 0: Reset
0 - Clears the reset bit and allows the other registers to
function properly.
1 - Resets the device. While this bit is 1 reads of other
registers will be 0 and writes to other registers will be
ignored. This bit is cleared only by writing a 0 to the
RESET bit.
248
uNOTE # 032
Page 3 of 42
Master Configuration Control Register
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Address = 177002
Bit 7: Port B Enable (PBE)
0 - Inhibits Port B from issuing an interrupt request and forces
tth Port B I/O lines into a high impedance state.
1 - Allows Port B to operate normally.
Bit 6: Counter/Timer 1 Enable (CT1E)
0 - Inhibits Counter/Timer 1 from issuing an interrupt request
and clears the Count In Progress (CIP) flag. All trigger
inputs are ignored.
1 - Allows Counter/Timer 1 to operate normally.
Bit 5: Counter/Timer 2 Enable (CT2E)
Provides the same functions for Counter/Timer 2 that CT1E does
for Counter/Timer 1.
Bit 4: Port C and Counter/Timer 3 Enable (PCE) and (CT3E)
Provides the same functions for Port C that PBE does for Port B
and the same functions for Counter/Timer 3 that CT1E does for
Counter/Timer 1.
Bit 3: Port Link Control (PLC)
0 - Allows Ports A and B to operate independently.
1 - Links Ports A and B to form a 16-bit port. In this mode
Port A's handshake and command and status registers are
used. Port B is specified as a bit port. This bit must be
set before the ports are enabled.
Bit 2: Port A Enable (PAE)
Provides the same functions for Port A that PBE provides for
Port B.
Bits 1,0: Counter/Timer Link Controls
These two bits specify how Counter/Timers 1 and 2 are linked
according to the following table:
249
uNOTE # 032
Page 4 of 42
Bit 1 Bit 0
0 0 Counter/Timers are independent
0 1 C/T 1's output (inverted) gates C/T 2
1 0 C/T 1's output (inverted) triggers C/T 2
1 1 C/T 1's output (inverted) is C/T 2's count input
The Counter/Timers must be linked before they are enabled.
PORT SPECIFICATION REGISTERS
Ports A and B both utilize the following port specification registers:
Port Mode Specification Register
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177100
Port B = 177120
A RESET forces all of these bits to 0. All bits are read/write.
Bits 7,6: Port Type Select
These two bits specify the port type as defined by the
following table:
Bit 7 Bit 6
0 0 Bit port (No handshake)
0 1 Input port with handshake
1 0 Output port with handshake
1 1 Bidirectional port with handshake
Bit 5: Interrupt on Two Bytes (ITB)
0 - Indicates that Interrupt Pending (IP) should be set when
one byte of data is available for transfer. For an input
port IP is set when the Input Data Register is full. For an
output port IP is set when the Output Data Register is
empty.
1 - Indicates that IP should be set when two bytes of data are
available for transfer. For an input port IP is set when
both the Input Data Register and the Input Buffer Register
are full. For an output port IP is set when both the Output
Data Register and the Output Data Buffer are empty.
This bit must be set to zero for ports specified as bit
ports, single-buffered ports, or bidirectional ports.
250
uNOTE # 032
Page 5 of 42
Bit 4: Single Buffered (SB)
0 - Indicates that the port is double-buffered.
1 - Indicates the the port is single-buffered.
This bit is always 0 for bit ports.
Bit 3: Interrupt on Match Only (IMO)
0 - Port operates normally.
1 - An interrupt is generated when the data moved into the Input
Data Register or out of the Output Data Register matches the
pattern specification.
Bits 2,1: Pattern Mode Specification Bits
These bits define the operation of the pattern recognition logic
as shown by the following table:
Bit 2 Bit 1
0 0 Disable Pattern Match
0 1 AND Mode
1 0 OR Mode
1 1 OR-Priority Encoded Vector Mode
Bit 0: Latch on Pattern Match (LPM) or Deskew Timer Enable (DTE)
When a port is used as a bit port the LPM function is used.
When a port with handshake is used the DTE function is used.
LPM:
0 - Pattern matches are detected but the data read from the port
follows the port pins.
1 - When a pattern match is detected the input data at the port
is latched.
DTE:
0 - The deskew timer is not activated.
1 - The deskew timer is activated to perform delay functions as
set in the Port Handshake Specification Register.
Port Handshake Specification Register
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177102
Port B = 177122
251
uNOTE # 032
Page 6 of 42
These bits are ignored if the port is a bit port. A RESET forces all
bits to 0. All bits are read/write.
Bits 7,6: Handshake Type Specification Bits
These bits define the type of handshake a port will use as shown
by the following table:
Bit 7 Bit 6
0 0 Interlocked Handshake
0 1 Strobed Handshake
1 0 Pulsed Handshake
1 1 3-Wire Handshake
The Pulsed and 3-Wire Handshakes must not be specified for
bidirectional ports. Only one port at a time may use the Pulsed
Handshake. If one port uses the 3-Wire Handshake the other port
must be specified as a bit port.
Bits 5,4,3: REQUEST/WAIT Specification Bits (RWS)
The WAIT function is not implemented on the KXT11-C. These bits
define the utilization of the REQUEST line as shown by the
following table:
Bit 5 Bit 4 Bit 3
0 0 0 REQUEST disabled
0 0 1 Not supported
0 1 1 Not supported
1 0 0 Special REQUEST
1 0 1 Output REQUEST
1 1 1 Input REQUEST
Only Port A may use the REQUEST capability - Port B must be
programmed as a bit port.
Bits 2,1,0: Deskew Time Specification Bits
These bits specify the amount of deskew time to be provided for
output data. They define the minimum number of Peripheral Clock
(PCLK) cycles of delay between the output of a new byte of data
and the handshake logic indicating that new data is available.
PCLK = 250 ns. 0 PCLK cycles are chosen by setting DTE=0 in the
Port Mode Specification Register.
252
uNOTE # 032
Page 7 of 42
Bit 2 Bit 1 Bit 0 PCLK cycles
0 0 0 2
0 0 1 4
0 1 0 6
0 1 1 8
1 0 0 10
1 0 1 12
1 1 0 14
1 1 1 16
Port Command and Status Register
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177020
Port B = 177022
A RESET forces ORE to 1 and all other bits to 0. All bits are
readable and four are writeable.
Bit 7: Interrupt Under Service (IUS)
0 - Cleared to indicate that the port is not servicing an
interrupt.
1 - Indicates that that the port has been recognized by an
interrupt acknowledge sequence.
Bit 6: Interrupt Enable (IE)
0 - Interrupt logic disabled. The port is unable to request an
interrupt or to respond to an interrupt acknowledge.
1 - Interrupt logic operates normally.
Bit 5: Interrupt Pending (IP)
0 - Cleared to indicate that the port does not require service.
1 - Set to indicate the port needs service because of a pattern
match, a handshake, or an error.
Bits 7, 6, and 5 are written using the following codes:
253
uNOTE # 032
Page 8 of 42
Bit 7 Bit 6 Bit 5
0 0 0 Null code
0 0 1 Clear IP and IUS
0 1 0 Set IUS
0 1 1 Clear IUS
1 0 0 Set IP
1 0 1 Clear IP
1 1 0 Set IE
1 1 1 Clear IE
Bit 4: Interrupt Error (ERR)
This bit is set to 1 when using a a bit port with pattern match
enabled if a second match occurs before the previous match is
acknowledged. This is a read-only bit.
Bit 3: Output Data Register Empty (ORE)
A status bit that indicates when an output port's Output Data
Register is empty. This bit can only be cleared by writing to
the data register. This is a read-only bit.
Bit 2: Input Data Register Full (IRF)
A status bit that indicates if an input port's Input Data
Register is full. This bit can only be cleared by reading the
Input Data Register. This is a read-only bit.
Bit 1: Pattern Match Flag (PMF)
If the port pattern match logic is enabled this bit will
indicate when a match is detected. This bit is read-only.
Bit 0: Interrupt on Error (IOE)
0 - Disables the generation of an interrupt if an error occurs
within the pattern match logic.
1 - Enables the generation of an interrupt if an error occurs
within the pattern match logic.
This bit is valid only for bit ports with pattern match logic
enabled. It is ignored by ports with handshake and should be
programmed to 0.
BIT PATH DEFINITION REGISTERS
Each port has a set of these registers. Only the four least significant
bits are valid in the port C registers.
254
uNOTE # 032
Page 9 of 42
Data Path Polarity Registers
These registers define whether the bits in a port are inverting or
non-inverting. These bits are cleared by a RESET and are read/write.
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177104
Port B = 177124
Port C = 177012
0 = Non-inverting
1 = Inverting
Date Direction Registers
These registers are ignored by ports with handshake. For bit ports
they define the data direction for each bit. These bits are cleared
by a RESET and are read/write.
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177106
Port B = 177126
Port C = 177014
0 = Output bit
1 = Input bit
Special I/O Control Registers
These registers supply special characteristics to the port's data
paths. A RESET clears all bits to 0. All bits are read/write.
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177110
Port B = 177130
Port C = 177016
0 = Normal Input or Output
1 = Input with 1's catcher
255
uNOTE # 032
Page 10 of 42
PATTERN DEFINITION REGISTERS
These registers are used collectively to specify the match pattern for a
port. A RESET clears all bits to 0. All bits are read/write.
Pattern Polarity Registers (PPR)
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177112
Port B = 177132
Pattern Transition Registers (PTR)
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177114
Port B = 177134
Pattern Mask Registers (PMR)
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177116
Port B = 177136
The pattern specification for each bit is shown in the following
table:
PPR PTR PMR
0 0 0 Bit masked off
0 1 0 Any transition
1 0 0 Zero
1 0 1 One
1 1 0 One to zero transition
1 1 1 Zero to one transition
PORT DATA REGISTERS
Ports A and B have a data path that consists of three registers: an
Input Data Register, and Output Data Register, and a Buffer Register.
The Buffer Register is used to buffer the input or output data of a port
with handshake. It is also used by bit ports to latch data when pattern
matching is enabled.
256
uNOTE # 032
Page 11 of 42
Port A and B Data Registers
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177114
Port B = 177134
The Port C data register consists of two registers: an Input Data
register and an Output Data register. Because Port C is only 4 bits
wide the least significant four bits of the data register are used for
the data path. The four most significant bits are used as a write-
protect mask for the four least significant bits.
Port C Data Register
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
| | | | ^ ^ ^ ^
| | | | | | | |
| | | +---|---|---|---+
| | +-------|---|---+
| +-----------|---+
+---------------+
Bits 7,6,5,4: 0 = Writing of corresponding LSB enabled
1 = Writing of corresponding LSB inhibited
Port C = 177036
COUNTER/TIMER CONTROL REGISTERS
Each counter/timer has a set of Counter/Timer Control registers to
specify the operation of the counter/timers.
Counter/Timer Mode Specification Registers
These registers define the mode of operation for the counter/timers
and specify the external control and status lines to provide for it.
A RESET clears all bits to 0. All bits are read/write.
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Counter/Timer 1 = 177070
Counter/Timer 2 = 177072
Counter/Timer 3 = 177074
257
uNOTE # 032
Page 12 of 42
Bit 7: Continuous/Single Cycle
0 - When the counter reaches 0 the countdown sequence is
terminated.
1 - When the counter reaches 0 the time constant value is
reloaded and the countdown sequence is repeated.
Bit 6: External Output Enable (EOE)
0 - No external access.
1 - The output of the counter/timer is available on the I/O pin
associated with that counter/timer. (See table 2 for pin
assignments.)
Bit 5: External Count Enable (ECE)
0 - No external access.
1 - The I/O line of the port associated with the counter/timer
is used as an external counter input. (See table 2 for pin
assignments.)
Bit 4: External Trigger Enable (ETE)
0 - No external access
1 - The I/O line of the port associated with the counter/timer
is used as a trigger input to the counter/timer. (See
table 2 for pin assignments.)
Bit 3: External Gate Enable (EGE)
0 - No external access
1 - The I/O line of the port associated with the counter/timer
is used as an external gate input to the counter/timer.
This allows the external line to suspend/continue the
countdown in progress by toggling the line. (See table
2 for pin assignments.)
Bit 2: Retrigger Enable Bit (REB)
0 - Triggers (external or internal) that occur during a
countdown sequence are ignored.
1 - Triggers that occur during a countdown sequence cause a
new countdown to begin.
Bits 1,0: Output Duty Cycle Selects
These two bits select the output duty cycle as shown in the
following table:
258
uNOTE # 032
Page 13 of 42
Bit 1 Bit 0
0 0 Pulse Output
0 1 One-Shot Output
1 0 Square Wave Output
1 1 Do not use
See figure 2 for a description of each output duty cycle.
Counter/Timer Command and Status Registers
Each counter/timer contains a command and status register for
controlling the operation of the counter/timer. A RESET clears all
bits to 0.
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Counter/Timer 1 = 177024
Counter/Timer 2 = 177026
Counter/Timer 3 = 177030
Bit 7: Interrupt Under Service (IUS)
The operation of the this bit is the same as the IUS bit
described on page *.
Bit 6: Interrupt Enable (IE)
The operation of the this bit is the same as the IE bit
described on page *.
Bit 5: Interrupt Pending (IP)
This bit is set to 1 to indicate that the counter/timer needs
to be serviced. It is automatically set to 1 each time the
counter/timer reaches its terminal count.
The IUS, IE, IP bits are written by using the codes shown in the
following table:
Bit 7 Bit 6 Bit 5
0 0 0 Null code
0 0 1 Clear IP and IUS
0 1 0 Set IUS
0 1 1 Clear IUS
1 0 0 Set IP
1 0 1 Clear IP
1 1 0 Set IE
1 1 1 Clear IE
259
uNOTE # 032
Page 14 of 42
Bit 4: Interrupt Error (ERR)
This bit is set to indicate that the counter/timer has reached
a terminal count before the previous terminal count has been
serviced.
Bit 3: Read Counter Control (RCC)
Writing this bit to a 1 causes the contents of the Counter/Timer
Current Count Register (CCR), which normally follows the down-
counter, to be frozen until the least-significant byte of the
CCR is read.
Bit 2: Gate Command Bit (GCB)
0 - Halts the countdown sequence.
1 - Starts or resumes the countdown sequence.
Bit 1: Trigger Command Bit (TCB)
When written with a 1, this bit causes the down-counter to be
loaded with the time constant value and a countdown sequence
to be initiated.
Bit 0: Count in Progress (CIP)
This status bit is set to 1 to indicate that a countdown
sequence is in progress. It is automatically set to 0 when
the down-counter reaches 0.
Counter/Timer Time Constant Registers
These registers contain the time constant value that is loaded into
the down-counter when a trigger is detected. These registers are 16
bits wide and are accessed as two 8-bit registers. (Bit 7 of the
most-significant byte is bit 15 of the Time Constant register). A
RESET does not effect these registers.
Bit 15 Bit 0
<------------- MSB -------------> <------------- LSB ------------->
+-------------------------------+ +-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+ +-------------------------------+
Counter/Timer 1 MSB = 177054 Counter/Timer 1 LSB = 177056
Counter/Timer 2 MSB = 177060 Counter/Timer 2 LSB = 177062
Counter/Timer 3 MSB = 177064 Counter/Timer 3 LSB = 177066
260
uNOTE # 032
Page 15 of 42
Counter/Timer Current Count Registers
These 16-bit registers follow the contents of the appropriate down-
counter until a 1 is written into the RCC register. At that time the
contents of the CCR are frozen until the least-significant byte of the
CCR is read. A RESET forces the CCR to follow the down-counter again.
Bit 15 Bit 0
<------------- MSB -------------> <------------- LSB ------------->
+-------------------------------+ +-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+ +-------------------------------+
Counter/Timer 1 MSB = 177040 Counter/Timer 1 LSB = 177042
Counter/Timer 2 MSB = 177044 Counter/Timer 2 LSB = 177046
Counter/Timer 3 MSB = 177050 Counter/Timer 3 LSB = 177052
INTERRUPT RELATED REGISTERS
These registers contain the interrupt vectors output during an interrupt
acknowledge sequence. Registers are provided for Port A, Port B, one to
be shared by the Counter/Timers. Another register is provided to
indicate which devices need service in a polled environment.
Interrupt Vector Registers
These vectors contain the vector output when the source of an
interrupt is acknowledged. If Master Interrupt Enable = 1 then the
vector register returns status when read according to the following
table:
Port Vector Status
OR-Priority Encoded Vector Mode:
Bit 3 Bit 2 Bit 1
x x x Encodes the number of the highest-priority
bit with a match
All other modes:
Bit 3 Bit 2 Bit 1
ORE IRF PMF Normal
0 0 0 Error
Counter/Timer Status
Bit 2 Bit 1
0 0 Counter/Timer 3
0 1 Counter/Timer 2
1 0 Counter/Timer 1
1 1 Error
261
uNOTE # 032
Page 16 of 42
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Port A = 177004
Port B = 177006
Counter/Timers = 177010
The native firmware of the KXT11-C initializes these interrupt vectors
to the following values:
Port A = 200
Port B = 204
Counter/Timers = 210
Current Vector Register
When read, this register returns the interrupt vector that would have
been output by the device during an interrupt acknowledge cycle if its
IEI input had been high. The vector returned corresponds to the
highest priority IP independent of IUS. The order of priority is:
Counter/Timer 3, Port A, Counter/Timer 2, Port B, Counter/Timer 1. If
no enabled interrupts are pending, a pattern of ones is returned.
This is useful in a polled environment.
+-------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-------------------------------+
Address = 177076
I/O BUFFER CONTROL REGISTER
The PIO chip is protected from the connector by a set of buffers. These
buffers comply with the IEEE 488 electrical standards. The buffers
allow the ports to configured as inputs or outputs. They also allow the
ports to be configured as open collectors or active pull-ups.
+---------------------------------------------------------------------+
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---------------------------------------------------------------------+
Address = 177140
Bit 15: PCTT (Cleared on RESET)
0 - Configures the Port C drivers for open collector
1 - Configures the Port C drivers for active pull-up
262
uNOTE # 032
Page 17 of 42
Bit 14: PABTT (Cleared on RESET)
0 - Configures the Port A and B drivers for open collector
1 - Configures the Port A and B drivers for active pull-up
Bits 13:10: PC DIR (Cleared on RESET)
0 - Port C bit is a receiver
1 - Port C bit is a driver
Bit 9: PAHN DIR (Cleared on RESET)
0 - Port A high nibble bits (4:7) are receivers
1 - Port A high nibble bits are drivers
Bit 8: PALN DIR (Cleared on RESET)
0 - Port A low nibble bits (0:3) are receivers
1 - Port A low nibble bits are drivers
Bits 7:0: PB DIR (Cleared on RESET)
0 - Port B bit is a receiver
1 - Port B bit is a driver
PROGRAMMING THE I/O PORTS
This section will describe how to program the I/O ports and provide
example programs. In particular this section will describe how to use
the I/O ports in the following modes: as bit ports, as ports with
handshake, in 16-bit linked mode, and with the DMA controller. The use
of the pattern recognition logic will also be discussed.
Programming the I/O Ports as Bit Ports
Using the I/O ports as bit ports provides up to 20 lines for control and
status. Each bit in ports B and C may be independently configured to be
an input or an output. Port A must be configured on a nibble (4-bit)
basis.
Programming the PIO as a bit port is straight-forward. First, the Port
Mode Specification Register is used to select the port as a bit port
with/without pattern matching. Then the Bit Path Definition Registers
are used to determine the polarity, direction, and special
characteristics of the bits of the port. If pattern recognition is
enabled the Pattern Definition Registers must also be initialized. It
is then a simple matter to write to the output data buffer to provide
the correct control signals and to read the input data buffer to monitor
status.
263
uNOTE # 032
Page 18 of 42
The following program provides an example for using the PIO in the bit
mode:
.TITLE PIO1.MAC
;+
; This program provides an example of how to program the PIO's
; I/O ports as bit ports. This program utilizes the PIO
; loopback connector (Part #H3021 or 54-16227) which makes the
; following connections:
;
; A0 -- B0
; A1 -- B1
; .
; .
; A7 -- B7
; C0 -- C3
; C1 -- C2
;
; After this program has been assembled and linked on the
; development machine use the KUI utility of the KXT11-C Software
; Toolkit to load the program into the KXT11-C to execute as
; shown in this example:
;
; SET 2
; LOAD PIO1.SAV
; EXECUTE
; !ODT
; !
; !001152
; !R2/000000
; !1154/041101
; !001156/042103
; !001160/043105
; !001162/177507
; !001164/041101
; !001166/042103
; !001170/043105
; !001172/000107
; !001174/000000
; !
; EXIT
;
; A non-zero result in R2 indicates that an error has occurred. (Try
; running the test without the loopback connector). Location 1154 is
; the beginning of the output buffer. Location 1164 is the beginning
; of the input buffer.
;-
; Register Assignments
MIC == 177000
MCC == 177002
264
uNOTE # 032
Page 19 of 42
PAMODE == 177100
PAPOL == 177104
PADDIR == 177106
PASIO == 177110
PADATA == 177032
PBMODE == 177120
PBPOL == 177124
PBDDIR == 177126
PBSIO == 177130
PBDATA == 177034
IOCNTL == 177140
START::
MTPS #340 ; Inhibit recognition of
; interrupts
; Initialize PIO
MOVB #1,MIC ; Reset device and inhibit interrupt
; requests
CLRB MIC ; Enable device (interrupts still
; inhibited)
; Set-up Port A
CLRB PAMODE ; Port A: bit port, no pattern match
CLRB PAPOL ; Port A bits are non-inverting
CLRB PADDIR ; Port A bits are output bits
CLRB PASIO ; Normal output
; Set-up Port B
CLRB PBMODE ; Port B: bit port, no pattern match
CLRB PBPOL ; Port B bits are non-inverting
MOVB #377,PBDDIR ; Port B bits are input bits
CLRB PBSIO ; Normal input
; Set-up the PIO buffers
MOV #1400,IOCNTL ; configure the PIO buffers for
; A=output and B=input
; Initialize GPRs
MOV #OUTBUF,R0 ; Point to data to be output
MOV #INBUF,R1 ; Point to input data buffer
CLR R2 ; R2 will indicate error status
; Flush input buffer
TSTB PBDATA
; Enable Ports A and B and send the data
MOVB #204,MCC ; Enable ports A and B
265
uNOTE # 032
Page 20 of 42
1$: MOVB (R0)+,PADATA ; Move data out of Port A
NOP ; .
; .
MOVB PBDATA,(R1)+ ; and into Port B
; Test to see if done
TSTB (R0) ; IF (R0) is positive
BPL 1$ ; THEN transfer another byte
; ELSE check if data is valid
; Compare original data with received data
MOV #OUTBUF,R0 ; Point to output data buffer
MOV #INBUF,R1 ; Point to input data buffer
; Test to see if done
2$: TSTB (R0) ; IF (R0) is negative
BMI 3$ ; THEN done comparing
; ELSE do another compare
CMPB (R0)+,(R1)+ ; Compare bytes
BEQ 2$ ; IF bytes are equal
; THEN test another pair
; ELSE indicate error
INC R2 ; A non-zero value of R2 indicates
; an error
3$: BR . ; Branch here upon completion
OUTBUF: .BYTE 101,102,103,104,105,106,107,-1
.EVEN
INBUF: .BLKB 7
.END START
266
uNOTE # 032
Page 21 of 42
Programming the I/O Ports as Ports with Handshake
Ports A and B may be configured as ports with handshake to facilitate
transferring data on a byte-by-byte basis. Port C is used to provide
the handshake lines. In addition, Port C may use the REQUEST line to
utilize a DMA controller to transfer the data. See table 1 for a
description of the Port C handshake lines. Figure 1 shows how two PIOs
can be connected directly together to transfer data and the handshake
lines that are utilized.
PIO Handshake Lines
OUTPUT INPUT
+--------+ +--------+
| | | |
| |-----------------\ | |
| PIO | DATA \| PIO |
| | /| |
| |-----------------/ | |
| | | |
| DAV| ----------------->|ACKIN |
| ACKIN|<----------------- |RFD |
| | | |
+--------+ +--------+
- Figure 1 -
The handshakes that are available are: Interlocked, Strobed, Pulsed,
and 3-Wire. A short description of each handshake type follows:
When using the Interlocked Handshake any action by the PIO must be
acknowledged by the external device before the next action can take
place. In other words, an output port does not indicate that it has new
data available until the external device indicates that it is ready for
data. Likewise, and input port does not indicate that it is ready for
new data until the external device indicates that the previous byte of
data is no longer available, thereby acknowledging the input port's
acceptance of the last byte.
The Strobed Handshake uses external logic to "strobe" data into or out
of a port. In contrast to the Interlocked handshake, the signal
indicating that the port is ready for another data transfer operates
independently of the ACKIN input. External logic must ensure the data
transfers at the appropriate speed.
The Pulsed Handshake is used to interface to mechanical devices which
require data to be held for relatively long periods of time in order to
be gated in or out of the device. The logic is the same as the
Interlocked Handshake except that Counter/Timer 3 is linked to the
handshake logic to add the appropriate delays to the handshake lines.
The 3-Wire Handshake may be used so that one output port can communicate
267
uNOTE # 032
Page 22 of 42
to several input ports simultaneously. This is essentially the same as
the Interlocked Handshake except that two individual lines are used to
indicate when an input port is ready for data (RFD) and when it has
accepted data (DAC). Because this handshake requires three lines only
one port can use the 3-Wire Handshake at a time.
Port C Handshake Lines
Port C Bits
Port A/B Configuration Pin C3 Pin C2 Pin C1 Pin C0
+----------------------------------------------------------------------+
|Ports A & B = Bit Ports |Bit I/O |Bit I/O |Bit I/O |Bit I/O |
|-----------------------------------------------------------------------
|Port A = Input or Output |RFD or DAV |ACKIN |REQUEST |Bit I/O |
|(Interlocked, Strobed, | | |or Bit I/O | |
| or Pulsed Handshake)* | | | | |
|-----------------------------------------------------------------------
|Port B = Input or Output |REQUEST |Bit I/O |RFD or DAV |ACKIN |
|(Interlocked, Strobed, |or Bit I/O | | | |
| or Pulsed Handshake)* | | | | |
|-----------------------------------------------------------------------
|Port A or B = Input Port |RFD |DAV |REQUEST |DAC |
|(3-Wire Handshake) |(Output) |(Input) |or Bit I/O |(Output)|
|-----------------------------------------------------------------------
|Port A or B = Output Port |DAV |DAC |REQUEST |RFD |
|(3-Wire Handshake) |(Output) |(Input) |or Bit I/O |(Input) |
|-----------------------------------------------------------------------
|Port A or B = Bidirectional|RFD or DAV |ACKIN |REQUEST |IN/OUT |
|(Interlocked or Strobed | | |or Bit I/O | |
| Handshake) | | | | |
+----------------------------------------------------------------------+
* Both Ports A & B may be specified as input or output ports with
the Interlocked, Strobed, or Pulsed Handshakes at the same time
if neither uses REQUEST. Only one port can use the Pulsed
Handshake at a time.
- Table 1 -
When Ports A and B are configured as ports with handshake they must also
be configured as single- or double-buffered. Double-buffering a port
allows more time for the interrupt service routine to respond to a data
transfer. A second byte of data is input to or output from the port
before the interrupt for the first byte is serviced. A single-buffered
port is used where it is important to have byte-by-byte control over the
transfer or where it is important to enter the interrupt service routine
in a fixed amount of time after the data has been accepted/output.
The REQUEST line may also be used by ports with handshake. This control
line enables the PIO to signal the DMA controller of the KXT11-C that
the port wishes to transfer data without CPU intervention. The
operation of the REQUEST line is dependent on the Interrupt on Two Bytes
268
uNOTE # 032
Page 23 of 42
(ITB) bit in the Port Mode Specification Register. If ITB = 0 then the
REQUEST line goes active anytime a byte is available to transfer. If
ITB = 1 then the REQUEST line does not assert until two bytes are
available to transfer. The implementation of the PIO on the KXT11-C
requires that only Port A be used for DMA transfers. Since the REQUEST
line utilizes one of the Port C bits Port B must be programmed as a bit
port when Port A uses the REQUEST facility.
The following example programs display the capabilities of the PIO used
as a port with handshake:
.TITLE PIO2.MAC
; This program demonstrates the ability of the PIO to transfer data
; on a byte-by-byte basis. The program uses the Interlocked
; Handshake to transfer data from Port A to Port B. Both ports are
; configured as single-buffered. The PIO loopback connector (part
; #H3022 or 54-16227) or a functional equivalent is required to
; successfully run this program.
;
; After this program has been assembled and linked on the
; development machine use the KUI utility of the KXT11-C Software
; Toolkit to load the program into the KXT11-C to execute as
; shown in this example:
;
; SET 2
; LOAD PIO2.SAV
; EXECUTE
; !ODT
; !
; !001214
; !1262/065151
; !001264/066153
; !001266/067155
; !001270/070157
; !001272/000377
; !001274/065151
; !001276/066153
; !001300/067155
; !001302/070157
; !001304/000000
; !
; EXIT
;
; This verifies that the contents of the output buffer (location 1262
; were successfully transferred to the input buffer (location 1274).
;
; Register Assignments
MIC == 177000
269
uNOTE # 032
Page 24 of 42
MCC == 177002
PAVEC == 177004
PASTAT == 177020
PADATA == 177032
PAMODE == 177100
PAHDSH == 177102
PAPOL == 177104
PASIO == 177110
PBVEC == 177006
PBSTAT == 177022
PBDATA == 177034
PBMODE == 177120
PBHDSH == 177122
PBPOL == 177124
PBSIO == 177130
PCPOL == 177012
PCDDIR == 177014
IOCNTL == 177140
START::
MTPS #340 ; Inhibit recognition of interrupts
MOVB #1,MIC ; Reset device and inhibit interrupt
; requests from the PIO
CLRB MIC ; Enable device (interrupts still
; inhibited)
MOVB #200,PAVEC
MOV #OUT,@#200 ; Set up Port A interrupt vector
MOV #340,@#202 ; ... and PSW
MOVB #204,PBVEC
MOV #IN,@#204 ; Set up Port B interrupt vector
MOV #340,@#206 ; ... and PSW
; Set-up Port A
MOVB #220,PAMODE ; Port A: Output Port, single-buffered
CLRB PAHDSH ; Use interlock handshake
CLRB PAPOL ; Port A bits are non-inverting
CLRB PASIO ; Normal output
MOVB #300,PASTAT ; Enable Port A interrupts
; Set-up Port B
MOVB #120,PBMODE ; Port B: Input Port, single-buffered
CLRB PBHDSH ; Use interlock handshake
CLRB PBPOL ; Port B bits are non-inverting
CLRB PBSIO ; Normal input
MOVB #300,PBSTAT ; Enable Port B interrupts
270
uNOTE # 032
Page 25 of 42
; Set-up the Port C handshake lines.
; All handshake lines are configured as inputs - even
; if they aren't!
MOVB #377,PCDDIR ; Port C bits are inputs
; Set-up the PIO buffers
MOV #165400,IOCNTL ; configure the PIO buffers for A=out
; B=input, C0,C2=input, C1,C3=output
; Set-up data areas
MOV #OUTBUF,R0 ; Point to Output Buffer
MOV #INBUF,R1 ; Point to Input Buffer
; Enable Interrupts
MOVB #224,MCC ; Enable ports A, B, and C
MOVB #200,MIC ; Enable MIC
MTPS #0 ; Enable recognition of interrupts
; Start the first transfer
MOVB #200,PASTAT ; Set IP to initiate a transfer
BR . ; Wait here for the interrupts
OUT::
TSTB (R0) ; IF (R0) are negative
BMI 1$ ; THEN transfers are complete
; ELSE transfer another byte
MOVB (R0)+,PADATA ; Move byte to the Port A output data
; register
BR 2$
1$: MOVB #240,PASTAT ; Clear IP when done
2$: MOVB #140,PASTAT ; Clear IUS on each pass
RTI
IN::
MOVB PBDATA,(R1)+ ; Move byte from Port B input data
; register
MOVB #140,PBSTAT ; Clear IUS on each pass
RTI
OUTBUF: .BYTE 151,152,153,154,155,156,157,160,-1
.EVEN
INBUF: .BLKB 10
.END START
271
uNOTE # 032
Page 26 of 42
.TITLE PIO3.MAC
; This program is basically the same as PIO2.MAC with the
; with the exception that the ports are double-buffered.
; The PIO loopback connector (part #H3022 or 54-16227) or a
; functional equivalent is required to successfully run this program.
;
; After this program has been assembled and linked on the
; development machine use the KUI utility of the KXT11-C Software
; Toolkit to load the program into the KXT11-C to execute as
; shown in this example:
;
; SET 2
; LOAD PIO3.SAV
; EXECUTE
; !ODT
; !
; !001214
; !1272/065151
; !001274/066153
; !001276/067155
; !001300/070157
; !001302/000377
; !001304/065151
; !001306/066153
; !001310/067155
; !001312/070157
; !001314/000000
; !
; EXIT
;
; This verifies that the contents of the output buffer (location 1272
; were successfully transferred to the input buffer (location 1304).
;
; Register Assignments
MIC == 177000
MCC == 177002
PAVEC == 177004
PASTAT == 177020
PADATA == 177032
PAMODE == 177100
PAHDSH == 177102
PAPOL == 177104
PASIO == 177110
PBVEC == 177006
PBSTAT == 177022
PBDATA == 177034
PBMODE == 177120
272
uNOTE # 032
Page 27 of 42
PBHDSH == 177122
PBPOL == 177124
PBSIO == 177130
PCPOL == 177012
PCDDIR == 177014
IOCNTL == 177140
START::
MTPS #340 ; Inhibit recognition of interrupts
MOVB #1,MIC ; Reset device and inhibit interrupt
; requests from the PIO
CLRB MIC ; Enable device (interrupts still
; inhibited)
MOVB #200,PAVEC
MOV #OUT,@#200 ; Set up Port A interrupt vector
MOV #340,@#202 ; ... and PSW
MOVB #204,PBVEC
MOV #IN,@#204 ; Set up Port B interrupt vector
MOV #340,@#206 ; ... and PSW
; Set-up Port A
MOVB #240,PAMODE ; Port A: Output Port, double-buffered
CLRB PAHDSH ; Use interlock handshake
CLRB PAPOL ; Port A bits are non-inverting
CLRB PASIO ; Normal output
MOVB #300,PASTAT ; Enable Port A interrupts
; Set-up Port B
MOVB #140,PBMODE ; Port B: Input Port, double-buffered
CLRB PBHDSH ; Use interlock handshake
CLRB PBPOL ; Port B bits are non-inverting
CLRB PBSIO ; Normal input
MOVB #300,PBSTAT ; Enable Port B interrupts
; Set-up the Port C handshake lines.
; All handshake lines are configured as inputs - even
; if they aren't!
MOVB #377,PCDDIR ; Port C bits are inputs
; Set-up the PIO buffers
MOV #165400,IOCNTL ; configure the PIO buffers for A=out
; B=input, C0,C2=input, C1,C3=output
; Set-up data areas
MOV #OUTBUF,R0 ; Point to Output Buffer
MOV #INBUF,R1 ; Point to Input Buffer
273
uNOTE # 032
Page 28 of 42
; Enable Interrupts
MOVB #224,MCC ; Enable ports A, B, and C
MOVB #200,MIC ; Enable MIC
MTPS #0 ; Enable recognition of interrupts
; Start the first transfer
MOVB #200,PASTAT ; Set IP to initiate a transfer
BR . ; Wait here for the interrupts
OUT::
TSTB (R0) ; IF (R0) are negative
BMI 1$ ; THEN transfers are complete
; ELSE transfer another byte
MOVB (R0)+,PADATA ; Move 1st byte to the Port A output
; data register
MOVB (R0)+,PADATA ; Move 2nd byte to the Port A buffer
; register
BR 2$
1$: MOVB #240,PASTAT ; Clear IP when done
2$: MOVB #140,PASTAT ; Clear IUS on each pass
RTI
IN::
MOVB PBDATA,(R1)+ ; Move 1st byte from Port B input data
; register
MOVB PBDATA,(R1)+ ; Move 2nd byte from Port B buffer
; register
MOVB #140,PBSTAT ; Clear IUS on each pass
RTI
OUTBUF: .BYTE 151,152,153,154,155,156,157,160,-1
.EVEN
INBUF: .BLKB 10
.END START
274
uNOTE # 032
Page 29 of 42
; This example shows something a little more practical - one
; KXT11-C transferring data to another. Two programs follow:
; one accepts data through Port B using the double-buffered
; mode (PIO4I.MAC); the second one sends data out of Port A
; using the double buffered mode (PIO4O.MAC). In order to
; successfully run these programs the KXT11-Cs must be connected
; by a "straight-thru" ribbon cable which is given a half twist.
; In other words, it should make the same connections that the
; PIO loopback connector does. (A1-B1,A2-B2,...A7-B7,C0-C3,C1-C2).
;
; Each program should be assembled and linked separately on the
; development machine. Then use the KUI utility of the KXT11-C
; Software Toolkit to load the programs into the KXT11-Cs to execute
; as shown in this example:
;
; SET 3
; LOAD PIO4I.SAV
; EXECUTE
; SET 2
; LOAD PIO4O.SAV
; EXECUTE
; SET 3
; !ODT
; !
; !001130
; !1152/065151
; !001154/066153
; !001156/067155
; !001160/070157
; !001162/000000
; !
; EXIT
;
; This verifies that the data was successfully transferred to
; the input buffer of KXT11-C #3.
;
;-------------------------------------------------------------------
;-------------------------------------------------------------------
.TITLE PIO4I.MAC
; Register Assignments
MIC == 177000
MCC == 177002
PBVEC == 177006
PBSTAT == 177022
PBDATA == 177034
PBMODE == 177120
PBHDSH == 177122
PBPOL == 177124
PBDDIR == 177126
275
uNOTE # 032
Page 30 of 42
PBSIO == 177130
PCDDIR == 177014
IOCNTL == 177140
START::
MTPS #340 ; Inhibit recognition of interrupts
MOVB #1,MIC ; Reset device and inhibit interrupt
; requests from the PIO
CLRB MIC ; Enable device (interrupts still
; inhibited)
MOVB #204,PBVEC
MOV #IN,@#204 ; Set up Port B interrupt vector
MOV #340,@#206 ; ... and PSW
MOVB #140,PBMODE ; Port B: Input Port, double-buffered
CLRB PBHDSH ; Use interlock handshake
CLR PBPOL ; Port B bits are non-inverting
CLR PBSIO ; Normal input
MOVB #300,PBSTAT ; Enable Port B interrupts
MOVB #377,PCDDIR ; Port C bits are inputs
MOV #165400,IOCNTL ; configure the PIO buffers for A=out
; B=input, C0,C2=input, C1,C3=output
MOV #INBUF,R1 ; Point to input data buffer
MOVB #220,MCC ; Enable ports B and C
MOVB #200,MIC ; Enable MIC
MTPS #0 ; Enable recognition of interrupts
BR . ; Wait here for the interrupts
IN::
MOVB PBDATA,(R1)+ ; Move 1st byte from Port B input data
; register
MOVB PBDATA,(R1)+ ; Move 2nd byte from Port B buffer
; register
MOVB #140,PBSTAT ; Clear IUS on each pass
RTI
INBUF: .BLKB 10
.END START
276
uNOTE # 032
Page 31 of 42
;-----------------------------------------------------------------
;-----------------------------------------------------------------
.TITLE PIO4O.MAC
; Register Assignments
MIC == 177000
MCC == 177002
PAVEC == 177004
PASTAT == 177020
PADATA == 177032
PAMODE == 177100
PAHDSH == 177102
PAPOL == 177104
PADDIR == 177106
PASIO == 177110
PCPOL == 177012
PCDDIR == 177014
IOCNTL == 177140
START::
MTPS #340 ; Inhibit recognition of interrupts
MOVB #1,MIC ; Reset device and inhibit interrupt
; requests from the PIO
CLRB MIC ; Enable device (interrupts still
; inhibited)
MOVB #200,PAVEC
MOV #OUT,@#200 ; Set up Port A interrupt vector
MOV #340,@#202 ; ... and PSW
MOVB #240,PAMODE ; Port A: Output Port, double-buffered
CLRB PAHDSH ; Use interlock handshake
CLR PAPOL ; Port A bits are non-inverting
CLR PASIO ; Normal output
MOVB #300,PASTAT ; Enable Port A interrupts
MOVB #377,PCDDIR ; Port C bits are inputs
MOV #165400,IOCNTL ; configure the PIO buffers for A=out
; B=input, C0,C2=input, C1,C3=output
MOV #OUTBUF,R0 ; Point to output data buffer
MOVB #24,MCC ; Enable ports A and C
MOVB #200,MIC ; Enable MIC
MTPS #0 ; Enable recognition of interrupts
277
uNOTE # 032
Page 32 of 42
MOVB #200,PASTAT ; Set IP to initiate a transfer
BR . ; Wait here for the interrupts
OUT::
TSTB (R0) ; IF (R0) are negative
BMI 1$ ; THEN all data has been transferred
; ELSE do another transfer
MOVB (R0)+,PADATA ; Move 1st byte to the Port A output
; data register
MOVB (R0)+,PADATA ; Move 2nd byte to the Port A buffer
; register
BR 2$
1$: MOVB #240,PASTAT ; Clear IP when done
2$: MOVB #140,PASTAT ; Clear IUS on each pass
RTI
OUTBUF::.BYTE 151,152,153,154,155,156,157,160,-1
.END START
278
uNOTE # 032
Page 33 of 42
; The following two programs demonstrate how the DTC may be used
; to transfer data from the PIO to KXT11-C local memory. DTC
; transfers may only be accomplished using Port A of the PIO.
; It is not possible to properly connect two PIOs with a ribbon
; cable because the handshake lines will not align correctly when
; connecting Port A to Port A. Therefore it is necessary to build
; a cable that makes the following connections:
;
; Input Port A Output Port A
; A0 <--------> A0
; A1 <--------> A1
; . .
; . .
; A7 <--------> A7
;
; C2 <--------> C3
; C3 <--------> C2
;
; It is also necessary to place a jumper between posts M48 and M49
; so that the REQUEST line from the PIO may signal the DTC. For more
; information about programming the DTC please refer to Micronote 18.
;
; After each program has been assembled and linked on the
; development machine use the KUI utility of the KXT11-C Software
; Toolkit to load the programs into a KXT11-C to execute as
; shown in this example:
;
; SET 3
; LOAD PIO5I.SAV
; EXECUTE
; SET 2
; LOAD PIO5O.SAV
; EXECUTE
; SET 3
; !ODT
; !
; !001140
; !1140/000777
; !001142/065151
; !001144/066153
; !001146/067155
; !001150/070157
; !001152/001602
; !
;
; Examining the contents of the input buffer (location 1142)
; verifies that the data was successfully transferred.
;
;------------------------------------------------------------
;
;------------------------------------------------------------
.TITLE PIO5I.MAC
279
uNOTE # 032
Page 34 of 42
; This program transfers data from Port A of the PIO
; to local memory by utilizing the DTC
; Register Assignments
MMREG == 174470
CMDREG == 174454
CASTF1 == 174444
CAOF1 == 174440
MIC == 177000
MCC == 177002
PAVEC == 177004
PASTAT == 177020
PADATA == 177032
PAMODE == 177100
PAHDSH == 177102
PAPOL == 177104
PADDIR == 177106
PASIO == 177110
PCPOL == 177012
PCDDIR == 177014
IOCNTL == 177140
START::
MTPS #340 ; Inhibit recognition of interrupts
; Initialize the DTC - for more information on the DTC
; refer to Micronote #18.
MOVB #154,MMREG ; Load Master Mode Reg to Disable DTC
CLRB CMDREG ; Reset the DTC
MOV #0,CASTF1 ; Load the CH1 Register SEG/TAG
MOV #RELOAD,CAOF1 ; Load the CH1 Register Offset
MOVB #155,MMREG ; Load Master Mode Reg to Enable DTC
MOVB #241,CMDREG ; Start Chain Channel 1
; Initialize the PIO
MOVB #1,MIC ; Reset device and inhibit interrupt
; requests from the PIO
CLRB MIC ; Enable device (interrupts still
; inhibited)
; Set-up Port A
MOVB #120,PAMODE ; Port A: Input Port, single-buffered
MOVB #70,PAHDSH ; Use interlock handshake, input
; REQUEST
CLR PAPOL ; Port A bits are non-inverting
CLR PASIO ; Normal input
280
uNOTE # 032
Page 35 of 42
MOVB #2,PCPOL ; Invert pin C1 - this is the line
; that is used for the REQUEST signal
MOVB #377,PCDDIR ; Port C bits are inputs
MOV #164377,IOCNTL ; configure the PIO buffers for A=in
; B=output, C0,C2=input, C1,C3=output
MOV #INBUF,R1 ; Point to input data buffer
MOVB #24,MCC ; Enable ports A and C
BR . ; Wait here while the DMA transfers
; take place
INBUF: .BLKB 10
; Chain Load Region
RELOAD: .WORD 001602 ; Reload Word
