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Note 30.0 PMI on KDJ11-B and MSV11-J No replies
FURILO::GIORGETTI 587 lines 21-AUG-1985 23:13
--------------------------------------------------------------------------------
+---------------+ +-----------------+
| d i g i t a l | | uNOTE # 030 |
+---------------+ +-----------------+
+----------------------------------------------------+-----------------+
| Title: The Private Memory Interconnect | Date: 28-Jun-85 |
| between the KDJ11-B and the MSV11-J | |
+----------------------------------------------------+-----------------+
| Originator: Peter Kent | Page 1 of 10 |
+----------------------------------------------------+-----------------+
Purpose
-------
This MicroNote describes the Private Memory Interconnect on the
MicroPDP-11/83 system. It is not intended to be a design guide for PMI,
since no devices other than the CPU and memory will make use of it.
General Description
-------------------
A MicroPDP-11/83 system consists of the KDJ11-B CPU and one or more
MSV11-J memories in a Q-bus backplane. The slots used for the CPU and
memory use the CD interconnect. In a MicroPDP-11/83 configuration, the
first 1 or 2 slots in a BA23 backplane (an 8 slot backplane with the
first 3 slots Q/CD) are reserved for MSV11-J memory. The CPU is put in
the third slot. The mechanical design of the signal pathways between
the CPU and memory were designed to prevent accidental interference
between the PMI and other devices that might be placed adjacent to the
CPU and memory. It is possible to have a single 2 Mb board in slot 1
followed by the CPU in slot 2. Putting the CPU after the memory ends
the PMI because the PMI signals from the CD side of the CPU board are
only on the component side of the CPU board.
"Private Memory Interconnect" is the addition of 14 unique signals to
the Q-bus. These new signals use the CD part of the backplane in a
Q-bus system for communications between the KDJ11-B CPU and one or two
MSV11-J memories. Only the CPU and memory may communicate over this bus
(hence PRIVATE). The Q-bus Data/Address lines are used for passsing
data and addresses between the CPU and memory. All other Q-bus
transactions proceed as before.
The PDP-11/84 Unibus system uses the KTJ11-B Unibus Adaptor, KDJ11-B
CPU, and one or two MSV11-J memories. No Q-bus devices may be
configured with the PDP-11/84 system. Five of the PMI signals are used
only with Unibus systems. All communications between Unibus devices and
the KTJ11-B occur according to the Unibus protocol. The KTJ11-B
provides the interface between PMI and Unibus protocols. This MicroNote
does not explain the details of the Unibus and PMI interaction.
227
uNOTE # 030
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What is PMI?
------------
To understand PMI it is necessary to describe some of the bus cycles
used by PMI and compare them with ordinary Q-bus cycles. There are 4
PMI cycles used in the MicroPDP-11/83 system:
DATI - Data word input. This cycle is used to read one or more 16
bit words from memory by the CPU.
DATIP - Data word input pause. This cycle is used to read one or
more 16 bit words from memory by the CPU. It is often used to
perform a read/modify/write cycle.
DATO - Data word ouput. This cycle is used to write a 16 bit word
to memory by the CPU.
DATOB - Data byte output. This cycle is used to write a byte to
memory by the CPU.
The KDJ11-B does not perform Block Mode reads or writes with memory.
Certain other Q-bus devices (such as the RDRX1 and RQDX2 controllers and
RQC25) perform Block Mode DMA with MSV11-P,MSV11-Q,AND MSV11-M memories.
The CPU monitors Block Mode transactions to keep its cache in order, but
it has no control over such transfers once it has relinquished control
of the bus to those devices.
REFERENCES
PMI signal definitions are listed at the end of this
MicroNote. All other signal definitions are as given in
the Microcomputer Products Handbook (EB 26078-41) or
Microsystems Handbook (EB 26085-41).
TWTBT, a Q-bus signal, is used somewhat differently during a PMI
transaction than during a normal Q-bus transaction. See the definitions
section for an explanation of this signal.
228
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NOTE
Few timing relationships are given here because it is
not necessary for a basic understanding of PMI. The
relationships that are given are a comparison to Q-bus
only. The prefix "T" refers to bus driver input and "R"
refers to bus receiver output. This helps to
distinguish between the device which issues a particular
signal and that of the receiver of the signal. If the
prefix "B" is used, it denotes a general term for the
signal on the bus without regard for its timing relation
with respect to sender or receiver (i.e. BSYNCH).
Address part of cycle
---------------------
The address portion of the MicroPDP-11/83 PMI cycles is the same for all
4 PMI cycles. It is listed here first and the description of the other
cycles follow.
1. For the first part of the cycle, the CPU gates ADDR, BBS7 (if the
I/O page is referenced), TWTBT, and TPBYT onto the Q-bus. The
combination of TWTBT and TPBYT (PMI signal) determine what type of
PMI transaction will take place - see Table 1 below. These signals
are asserted for a brief period after the assertion of TPBCYC.
Table 1
-------
BWTBT L PBYT L Description
H H DATI or DATBI Cycle
H L DATIP Cycle
L H DATO Cycle
L L DATOB Cycle
As noted above, Q-bus signals such as TWTBT are used differently
during a PMI cycle. TWTBT is not normally used during a DATI cycle,
for example.
2. Next, memory issues TPSSEL after receiving RADDR and RBS7. The CPU
receives RPSSEL. This part of the cycle indicates that the memory
is responding.
229
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3. If the CPU was the previous bus master and the previous cycle was a
Q-bus cycle, then the CPU must not assert TPBCYC or TSYNC until
after the negation of TSYNC and after the negation of RRPLY. If the
cycle was an interrupt service cycle, then the CPU must wait until
after the negation of RRPLY. This stipulation allows for other
Q-bus devices equal access to the bus. Also, if another Q-bus
device was previously bus master, then the CPU must not asssert
TPBCYC or TSYNC until after the negation of RSYNC - this is to make
sure RRPLY is negated long enough as per Q-bus protocol.
4. Now, if RPSSEL is asserted and if RPUBMEM is negated, the PMI master
proceeds with a PMI cycle. The negation of RPUBMEM indicates no
that no Unibus memory is responding - in other words a Q-bus PMI
cycle. Here is where the diffe- rence between Q-bus cycles and PMI
cycles becomes visible.
5. The CPU asserts TPBCYC after gating TADDR, TBS7, TPBYT, and TWTBT
onto the bus. The PMI master continues to gate TADDR, TBS7, and
TWTBT after the assertion of TPBCYC.
6. If at this point RPSSEL is negated, the system will revert to a
normal Q-bus cycle.
This describes the address portion of the PMI cycle for Q-bus only
systems.
DATI
----
When the CPU (KDJ11-B) is accessing memory for a PMI Data In Cycle, it
transfers 2 words. This takes advantage of the KDJ11-B restart overhead
to load a second 16-bit word into the cache on the CPU module. Listed
below equivalent Q-bus cycles are compared with PMI cycles under "Timimg
Comparisons". For the read cycle, 2 data words (one after another) are
latched into the MSV11-J data gate array and both words are placed on
the bus. Interestingly enough, either word may be selected to be placed
on the bus first. If the odd word is placed on the bus first, it is
followed by the preceding even word. For example, if a word at address
17362 is selected to be placed on the bus first, the next word
transferred will be from address 17360. If the even word is selected to
be placed on the bus first, the next odd word is then transferred
second. For example, if a word at address 17360 is selected to be
placed on the bus first, the next odd word is then transferred second.
For example, if a word at address 17360 is selected to be placed on the
bus, the next word transferred will be at address 17362.
230
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Using the MSV11-J memory as a normal Q-bus memory (disabling the PMI by
putting it after the CPU in the bus) and performing a read cycle, 2
words will be latched into the data gate array. However, only one word
is placed on the Q-bus.
1. At this point the address portion of the cycle is over. The memory
gates TDATA onto the bus after the assertion of RPBCYC.
2. Immediately after RPBCYC the memory enables the parity signals
TPHBPAR and TPLBPAR.
3. Memory asserts TPRDSTB immediately after the reception of RPBCYC.
4. The strobe signal TPRDSTB is negated by memory after the reception
of RPBCYC.
5. The memory gates the second data word onto the bus after TPRDSTB is
negated. Shortly after the parity in- formation is sent. Another
advantage is realized here: the second data word is transmitted
without the need of any further signals between the CPU and memory.
6. If the CPU has read 2 words, it negates TPBCYC after latching the
second data word.
7. After the negation of RPBCYC memory removes TDAT from the bus.
It becomes evident that there is an essential difference between normal
Q-bus transactions and PMI transactions. Q-bus transactions are all
based on handshaking. During a DATI Q-bus transaction, the memory
responds with BRPLY after BDIN from the processor. There must be the
signal between each device that the transaction has taken place. During
a PMI DATI transaction, there is only a strobe signal from the memory
saying that it is ready for the data. The only further communication
between the memory and CPU is the actual data transfer. Only upon the
transmission of the second possible data word is parity information sent
along with the second data word. No other memory-CPU signalling occurs.
231
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KDJ11-B MSV11-J
------- -------
Address Memory
--------------
o Gate Address
onto Address Lines ---------+
o Combination of |
TPBYT and TWTBT |
result in DATI Cycle +------> Decode Address
o Assert BBS7 if Address --------------
is in I/O Page +------- o TPSSEL asserted shows
| Memory is Selected
PMI Cycle Assertion <---------+
-------------------
o TPBCYC Indicates PMI Cycle
deasserts Address, BBS7 ------+
TPBYT,TWTBT Signals |
Address part of +-------> Data
cycle is finished ----
o TDATA, TPHBPAR, TPLBPAR
(Data and Parity) is
asserted onto Data Lines
o Memory strobes CPU by
Asserting TPRDSTB to tell
CPU Data is on the Bus
o The strobe signal
TPRDSTB is deasserted
+------- o The second data word and
| parity info are put on
PMI Cycle End <----------------+ the Data Lines
-------------
o CPU deasserts TPBCYC
to end PMI Cycle -------------+ Data
| ----
+------> o Memory removes
data from Bus
Timing Comparisons
------------------
At this point it would be interesting to make some timing comparisons
between Q-bus and PMI DATI transactions. Considering a Q-bus DATI
transaction, the cycle time (timing from BSYNCH to TRPLY ignoring
addressing time) is 510 ns for MSV11-M. The MSV11-M was chosen because
its cycle time does not include the ECC overhead of the MSV11-J. Add to
this 320 ns access time and this totals 830 ns to transfer 1 word from
memory to CPU. Now, if 2 words are to be transferred in this manner,
add another 300 ns due to delay between RRPLY and TSYNCH in order for
other Q-bus devices access to the bus. This results in 1130 ns total
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for a 2 word transfer using MSV11-M parity memory.
The MSV11-J memory access time is 417 ns. This is the time from RPBCYC
to PRDSTB. Fifty eight ns later, at the trailing edge of PRDSTB, the
CPU receives the second data word. This means that PMI is approx. 2.5
times faster than Q-bus on 2 word reads from memory to CPU. Remember,
this also accounts for the time the ECC requires to do its modified
Hamming code versus the MSV11-M parity check. For each 18 bits of
MSV11-J memory there are 6 bits used for ECC. This accounts for the
space needed on the MSV11-J for 2 Mb of memory whereas 4 Mb is possible
on the MSV11-Q on the same size board.
DATO (DATOB)
------------
The CPU uses DATO to transfer a single word (or byte for a DATOB cycle)
to memory. The address portion of the cycle is the same as for the DATI
and is described above.
1. The CPU determines what type of cycle (DATO or DATOB) by logically
combining TWTBT and TPBYT. During the address portion of the cycle,
these signals were used to indicate which type of PMI cycle was
selected.
2. Memory asserts TRPLY after RPBCYC.
3. After the assertion of TPBCYC, data is gated onto the bus by the
CPU.
4. The CPU asserts TPWTSTB after data is gated onto the bus.
5. Memory asserts TPSBFUL after RPWTSTB.
6. The CPU deasserts TPBCYC after negating TWTSTB.
7. The memory waits before it can accept another PMI cycle (or Q-bus
cycle) - then it deasserts TRPLY.
8. Memory negates TPSBFUL before it can accept another PMI (or Q-bus
cycle).
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KDJ11-B MSV11-J
------- -------
Address Memory
--------------
o Gate Addresses onto
Address Lines
o Combination of TPBYT
and TWTBT Result in
DATO Cycle
o Assert BBS7 if Address ------+
is in the I/O Page |
+-------> Decode Address
--------------
PMI Cycle Assertion +-------- o TPSSEL Shows
------------------- | Memory is address
o Assertion of TPBCYC <-------+ selected
indicates PMI Cycle
o CPU deasserts Address, BBS7,
TPBYT, TWTBT Signals -
Address Portion of Cycle ---+ Memory Responding
is finished | -----------------
+-------> o After reception of
RPBCYC, memory sends
Data TRPLY to CPU
----
o TDATA, TPHBPAR, TPLBPAR
(Data and Parity) is put
onto the Data Lines
o CPU then strobes the Reception of Data
Memory by asserting TPWTSTB --+ -----------------
+-------> o Memory asserts TPSBFUL
after reception of
+-------- RPWTSTB
|
PMI Cycle End <-------------+
-------------
o CPU deasserts TPBCYC
to indicate current Memory Cycle End
PMI Cycle is finished -------+ ----------------
+-------> o Memory waits for other
devices to claim Bus
before it can accept
another PMI Cycle - then
deasserts TRPLY
o Memory must negate
TPSBFUL before another
PMI Cycle can begin
234
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Timing Comparisons
------------------
Here is a comparison of a Q-bus DATO cycle with a PMI DATO cycle.
Looking at a Q-bus DATO transaction, the cycle time (timing from RSYNCH
to TRPLY) for MSV11-M is 550 ns. Comparing this to the MSV11-J DATO
cycle, the result of 223 ns is obtained. This figure is arrived at as
follows: 38 ns access time for the memory + 80 ns TPBCYC to TDATA + 75
ns TPWTSTB after data is on the bus + 30 ns to hold TPWTSB. Again the
speed advantage of PMI transactions over normal Q-bus transactions is
about 2.5 to 1.
DATIP
-----
The PMI Data In Pause cycle is identical to the DATI cycle except that
TPBYT is asserted with TADDR to indicate that the next cycle
(immediately following the current cycle) will be a data out cycle to
the same address.
PMI and Q-bus signal definitions
--------------------------------
Eight of the PMI signals are used in an MicroPDP-11/83 system, therefore
only those will be defined here. One Q-bus signal, BWTBT, is defined
here because it is used differently than during normal Q-bus
transactions.
PBYT L PMI Byte. When the CPU gates address onto the bus, it asserts
this signal with BWTBT to indicate the type of bus cycle (see
Table 1 above).
PBCYC L PMI bus cycle. The CPU asserts this signal at the start of
a PMI cycle and negates it at the end of that cycle.
PRDSTB L PMI read strobe. Memory asserts and negates this signal to
control data transfers during DATI cycles. The CPU latches
the received first word data on the negating edge of this
signal. The second word is latched after that without further
signalling.
PWTSTB L PMI Write Strobe. The CPU asserts this signal after gating
data onto the bus. The memory latches the data into its
write buffer after the leading edge of this pulse.
PSSEL L PMI slave selected. Memory asserts this signal whenever it
decodes its address on the Q-bus.
235
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PHBPAR L PMI high byte data parity. This signal is generated by PMI
memory during DATI cycles and provides odd parity for the high
byte data on the Q-bus.
PLBPAR L PMI low byte data parity. This signal is generated by PMI
memory during DATI cycles and provides even parity for the low
byte data.
PSBFUL L PMI memory buffer full. Memory asserts this signal during a
write cycle indicating that its write buffer is full and that
it cannot respond to another cycle request.
Q-bus signal
------------
BWTBT L Write byte (PMI write indication). In Q-bus systems, this
signal is used for Q-bus write cycles. For PMI transactions, the
CPU gates this signal with PBYT to indicate the type of PMI cycle.
See Table 1 above.
References
----------
Microcomputer Products Handbook EB-26078-41
Microsystems Handbook EB-26085-41
MSV11-M User Guide EK-MSV1M-UG-001
MSV11-Q User Guide EK-MSV1Q-UG-002
MSV11-J User Guide EK-MSV1J-UG-001
236
