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Note 18.0 KXT11-CA DMA Programming No replies
JAWS::KAISER 1117 lines 25-MAR-1985 09:22
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+---------------+ +-----------------+
| d i g i t a l | | uNOTE # 018 |
+---------------+ +-----------------+
+----------------------------------------------------+-----------------+
| Title: Programming the KXT11-CA DMA controller | Date: 28-DEC-84 |
+----------------------------------------------------+-----------------+
| Originator: Scott Tincher | Page 1 of 22 |
+----------------------------------------------------+-----------------+
The KXT11-CA intelligent I/O processor contains several user
programmable devices. One of these devices is a DMA transfer controller
(DTC). This article will describe the features of the DTC and provide
some programming examples. This article is intended for use by
individuals interested in programming the DTC using MACRO-11. DIGITAL
supplies a DTC device driver for those programmers using
MicroPower/Pascal. A working knowledge of MACRO-11 and of the KXT11-CA
is assumed.
FEATURES/CAPABILITIES
The DTC is addressable by the local T-11 microprocessor as an I/O
device. It is capable of performing DMA transfers between any of the
following addresses:
1) A 16-bit local address to a 16-bit local address
2) A 16-bit local address to a 22-bit global address
3) A 22-bit global address to a 16-bit local address
4) A 22-bit global address to a 22-bit global address
5) To/From channel A of the multiprotocol SLU
6) To/From the PIO chip
Word, high byte, and low byte transfers are supported locally. Only
word transfers are supported across the Q-bus.
The operations of the DTC are controlled by several internal registers.
It was designed with the capabilty of loading these registers directly
from memory thereby minimizing the amount of processor intervention
necessary to perform a DMA transaction. The area of memory where the
parameters for the DTC are stored is referred to as the chain table.
The local microprocessor need only load the address of the chain table
into the DTC and give a "start" command to initiate a DMA transfer.
DMA transactions may be initiated locally by the T11 or by the arbiter
CPU. If the transfer is initiated by the arbiter the command words and
transfer parameters are placed in the command registers of the two-port
RAM file. The local CPU will then initiate the DMA transaction using
the parameters supplied by the arbiter.
Page 2
The DTC consists of two identical channels. DMA transfers may be
interleaved between these two channels or interleaved between the DTC
and the T-11. It is also possible to select a "hog mode" that allows
the DMA transfer to run to completion without interruption.
The DTC supports three types of operations: Transfer, Search, and
Transfer-and-Search. As the name implies, Transfer operations move data
from a source to a destination. Search operations read data from a
source and compare the data to the pattern register. A mask register
allows the user to declare "don't care" bits. The Transfer-and-Search
operation combines the features of the Transfer and Search functions.
In this type of operation data is transferred between a source and
destination until the data transferred meets the match condition
specified in the Channel Mode register.
The DTC is capable of performing multiple DMA transactions without
processor intervention. This can be accomplished in two ways:
base-to-current reloading or chaining. Base-to-current reloading allows
the DTC to reload a portion of its registers before initiating a DMA
transfer. The reload operation occurs between internal registers so
there are no memory access related delays. This type of operation is
only practical in applications where data is continuously transferred
between the same addresses. Chaining allows all of the applicable
registers of the DTC to be reloaded from a new chain table. Therefore
this is a slower but more flexible alternative.
Upon completion of a DMA transfer the DTC may perform any combination of
the following options: Interrupt the local processor, perform
base-to-current reloading, or perform a chain reload. It may also
choose to take no action.
DTC REGISTERS
Among the internal registers of the DTC are two chip-level registers,
the Master Mode register and the Command register. These registers
control both channels of the DTC. In addition, each channel of the DTC
is controlled by several channel-level registers. For the sake of
completeness a brief description of these registers will be included
here. For a detailed description refer to the KXT11-CA Single Board
Computer User's Guide (EK-KXTCA-UG-001).
CHIP-LEVEL REGISTERS
Master Mode Register
The Master Mode register controls the chip-level interfaces. It is used
to:
- Enable/disable the DTC
- Select DTC/CPU interleaving
- Enable/disable asynch operation
- Enable/disable counter/timer interrupt request
- Enable/disable interrupt save vector
Page 3
Command Register
The command register is used to issue commands to the DTC channels such
as: Reset, Start Chain, etc.
CHANNEL-LEVEL REGISTERS
(Each of the following registers is present in each channel of the DTC)
Current Address Registers A and B (CARA, CARB)
CARA and CARB consist of two words, the segment/tag and the offset. The
segment/tag is used to indicate:
- Address bits <21:16> of the source (or destination)
- If the source (or destination) resides on the Q-bus
- Whether the source (or destination) address should be
incremented, decremented, or held constant
- Whether wait states should be included
The offset is used to indicate:
- Address bits <15:00>
Base Address Registers A and B (BARA, BARB)
BARA and BARB are identical to CARA and CARB. They are used to reload
CARA and CARB if base-to-current reloading is selected after a DMA
operation has terminated.
Current Operation Count Register (COPC)
This 16-bit register is used to specify the number of words (or bytes)
to be transferred during a DMA operation. The maximum word count is
obtained by programming this register with a zero.
Base Operation Count Register (BOPC)
This register is identical to the COPC register. It is used to reload
the COPC register when base-to-current reloading is selected.
Pattern and Mask Registers
The Pattern and Mask registers are used during Search and
Transfer-and-Search operations. The contents of the Pattern register
are compared to the read data to generate a "match" condition. The Mask
register is used to generate "don't care" bits. Setting a bit to '1' in
the Mask register specifies that the bit always matches.
Page 4
Status Register
The status register is a 16-bit read-only register which returns the
status of the following fields: Interrupts status, DTC status, Hardware
interface status, and Completion status.
Interrupt Vector and Interrupt Save Registers
The Interrupt Vector register contains the vector that is output during
an interrupt acknowledge cycle. When an interrupt occurs the contents
of the Interrupt Vector register and a part of the Status register are
stored in the Interrupt Save register. This allows a new vector to be
loaded during chaining so that a new DMA operation can be performed
before an interrupt acknowledge cycle occurs.
Channel Mode Register
The Channel Mode register consists of two words, channel mode high and
channel mode low. Channel mode low is used to indicate:
- The operation type (transfer, search,
transfer-and-search,bytes,words)
- Whether CARA (or CARB) defines the source (or destination)
- Transfer type (single, hog mode, interleaved)
- Completion options (interrupt CPU, base-to-current reload,
chain reload)
Channel mode high is used to:
- indicate match conditions
- mask the hardware requests for DMA operations
- cause the channel to request the bus for a DMA operation
Chain Address Register
The chain address register consists of two words, the segment/tag and
the offset. This register is used to point to the reload word, the
first word in a chain table. The segment/tag is used to indicate:
- Whether the reload word resides in Q-bus memory
- Whether the reload word resides in the Q-bus I/O page
- Address bits <21:16>
The offset is used to indicate:
- Address bits <15:00>
Page 5
PROGRAMMING THE DTC
Programming the DTC consists of three phases: Chip Initialization, Data
Transfer (or Search), and Termination. This section will provide a
general description of these phases.
CHIP INITIALIZATION
The Reset instruction is used to place the DTC in a known state. A
reset will clear the CIE, IP, SIP and WFB bits and set the CA and NAC
bits in the Channel Status registers. The Master Mode register will
also be cleared. Before a DMA operation is initiated the local CPU
loads the Master Mode register and the Chain Address register of the
appropriate channel of the DTC. The DTC fetchs any other parameters
that are necessary from a table located in system memory referred to as
the chain table. This minimizes the amount of CPU intervention
necessary to perform a DMA operation. The relationship of the Chain
Address register to the chain table is shown in Figure 1.
System
+---------------+ | Memory |
| | | |
| | |-------------------|
| DTC | +---------->| Reload Word |
| Channel 0/1 | | |-------------------|
| | | | |
| | | | DTC |
| | | | Register |
| +---------+ | | | Data |
| | Chain | | | | |
| | Address |--|----------+ |- - - - - - - - - -|
| | Reg. | | +----| New Chain Address |
| +---------+ | | |-------------------|
+---------------+ | | |
| | |
| | |
| | |
| |-------------------|
+--->| Reload Word |
|-------------------|
| |
| DTC |
| Register |
| Data |
| |
|-------------------|
| |
- Figure 1 -
Page 6
The first word in the chain table is the reload word. The reload word
is used to specify which registers are to be loaded for the pending DMA
operation. Bits <9:0> of the reload word correspond to the registers of
the DTC as shown in figure 2. Bits <15:10> are not used.
Reload Word
+---------------------------------------------------------------+
| x | x | x | x | x | x | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---------------------------------------------------------------+
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
| | | | | | | | | |
Current ARA -----------------+ | | | | | | | | |
Current ARB ---------------------+ | | | | | | | |
Current Op-Count --------------------+ | | | | | | |
Base ARA --------------------------------+ | | | | | |
Base ARB ------------------------------------+ | | | | |
Base Op-Count -----------------------------------+ | | | |
Pattern and Mask ------------------------------------+ | | |
Interrupt Vector ----------------------------------------+ | |
Channel Mode ------------------------------------------------+ |
Chain Address ---------------------------------------------------+
- Figure 2 -
Therefore if a bit in the reload word is set then the corresponding
register is to be reloaded from the chain table. Since all of the
registers are not applicable to each DMA operation the chain table may
be of variable length. ( i.e. The pattern and mask registers would not
be used in DMA operations that do not search the data.) It is NOT
correct to select a register in the reload word and subsequently load
that register with a dummy argument such as zero. The following are
examples of the relationship between the reload word and the chain
table.
| 9 8 7 6 5 4 3 2 1 0 |
|---------------------------------------------------------------|
| x | x | x | x | x | x | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|---------------------------------------------------------------|
| Current ARA Segment/Tag |
|---------------------------------------------------------------|
| Current ARA Offset |
|---------------------------------------------------------------|
| Current ARB Segment/Tag |
|---------------------------------------------------------------|
| Current ARB Offset |
|---------------------------------------------------------------|
| Current Op-Count |
|---------------------------------------------------------------|
| Channel Mode High |
|---------------------------------------------------------------|
| Channel Mode Low |
|---------------------------------------------------------------|
| |
Page 7
| 9 8 7 6 5 4 3 2 1 0 |
|---------------------------------------------------------------|
| x | x | x | x | x | x | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 |
|---------------------------------------------------------------|
| Current ARA Segment/Tag |
|---------------------------------------------------------------|
| Current ARA Offset |
|---------------------------------------------------------------|
| Current Op-Count |
|---------------------------------------------------------------|
| Pattern Register |
|---------------------------------------------------------------|
| Mask Register |
|---------------------------------------------------------------|
| Channel Mode High |
|---------------------------------------------------------------|
| Channel Mode Low |
|---------------------------------------------------------------|
| Chain Address Segment/Tag |
|---------------------------------------------------------------|
| Chain Address Offset |
|---------------------------------------------------------------|
| |
The DTC has been properly initialized once the chain table(s) have been
created and the Master Mode register and Chain Address Register for the
selected channel have been loaded.
DATA TRANSFER
The DTC may perform a DMA operation once it has been properly
initialized. A DMA operation may be initiated in one of four ways: by
software request, by hardware request, by loading a set software request
bit in the Channel Mode register during chaining, or as the result of a
command from the arbiter.
Software Request: The local CPU may initiate a DMA operation by writing
a 'software request' command followed by a 'start chain' command to the
Command register. The 'software request' command sets the software
request bit in the channel's Mode register. If either the SIP (second
interrupt pending) bit or the NAC (no auto-reload or chain) bit is set
in the channel's status register the DMA operation will not begin. The
SIP bit will be cleared when the channel receives an interrupt
acknowledge. The NAC bit will be cleared when the channel receives a
'start chain' command. The 'start chain' command initiates the DMA
operation after the registers of the selected channel are loaded from
the chain table. The 'start chain' command is ignored if the SIP bit or
the CA (Chain Abort) bit are set in the channel's status register. The
SIP bit was described above. The CA bit is cleared when the channel's
chain address register is reloaded.
Hardware Request: DMA operations may be started by applying a 'low' on
the channel's DREQ input. No details about this type of request will be
provided since they fall beyond the scope of this note.
Page 8
Starting After Chaining: If the software request bit of the channel's
Mode register is loaded during chaining the channel will perform the DMA
operation at the end of chaining.
Arbiter Request: The arbiter may interrupt the local CPU to request a
DMA operation. This is accomplished by passing parameters to load the
chain address register of channel 0 via the two-port RAM. The arbiter
loads register 2 of the TPR with the offset of the chain address
register and register 3 of the TPR with the segment/tag of the chain
address register. The DMA operation is then initiated by setting the
DMA Load bit (bit 1) in the TPR command register (register 0). Error
conditions will be returned in TPR register 1.
Information in the channel's Mode register determines what type of DMA
operation will be performed. The Channel Mode register consists of two
words, Channel Mode High and Channel Mode Low.
Bits <3:0> of the Channel Mode Low register select the type of DMA
operation. These bits determine whether the data should be transferred,
searched, or transferred-and-searched. Bit 4 is the flip bit. It is
used to determine which set of current address registers (CARA, CARB)
points to the source.
Bits <6:5> determine the transfer type. The types of DTC transfers are:
single transfer, demand dedicated with bus hold, demand dedicated with
bus release, and channel-to-channel demand interleave. Single transfer
is used with devices which transfer data at irregular intervals. A
single DMA transaction will occur each time a 'software request' command
is issued or the DREQ input is asserted. Demand dedicated with bus hold
is a software hog mode. This mode allows the DMA transaction to run to
completion as long as there is a valid op count and the DREQ input is
asserted. If the DREQ input is not asserted no DMA operations will
occur but the channel will retain bus control. Demand dedicated with
bus release is similar to demand dedicated with bus hold in that a DMA
transaction is allowed to run to completion if DREQ is asserted. If
DREQ is not asserted the DTC must release the bus thus allowing other
devices to obtain the bus. The operation performed by a
channel-to-channel demand interleave request depends on the state of bit
2 in the Master Mode register. If MM bit 2 is clear then control may be
passed between each channel of the DTC without the need to release the
bus. If MM bit 2 is set then the DTC must share the bus with the local
processor. The DTC will release the bus and then re-request it after
every DMA iteration.
Bits <1:0> of the Channel Mode High register are used to determine the
type of match control in Search and Transfer-and-Search operations. The
DTC is capable of generating a termination condition based on 'No
Match', 'Word Match', and 'Byte Match'.
Bit <4> of the Channel Mode High register causes the channel to request
the bus and perform transfers when it is set by a 'Software Request
Command' or a chain reload.
Page 9
TERMINATION OPTIONS
Bits <15:7> of the Channel Mode Low register control the termination
options. A DTC operation may be terminated in a number of ways. If the
Current Operation Count Register goes to zero then a Terminal Count (TC)
termination is generated. External logic may assert the End Of Process
(EOP) input of the DTC to generate an EOP termination at any time. In
addition, during a Search or Transfer-and-Search operation a match
condition may occur which generates a MC termination. Bits <15:7> allow
the DTC to perform a chain reload, a base-to-current reload, or to
interrupt the local processor if a TC, EOP, or MC termination condition
is encountered. If bits <15:7> are cleared then no special action is
initiated when a TC, EOP, or MC condition is encountered.
EXAMPLES
The following example programs were developed on a PDP-11/23+ system
with 256KB of memory using the RT-11 (version 5.1) operating system with
the KXT11-C Peripheral Processor Software Toolkit. These examples
assume the programmer is familiar with MACRO-11 and the KXT11-C
Peripheral Processor Toolkit.
Page 10
.TITLE EXAM1.MAC
; This program transfers data from local KXT11-C addresses to other
; local KXT11-C addresses. This program should be compiled and linked
; on the development system and then downloaded into the KXT11-C using
; the KXT11-C Software Toolkit. Once the program has been compiled
; and linked use the following KUI commands to execute it and verify
; its successfullness.
;
; .KUI
; KUI>SET n ! Where n is the appropriate KXT11-C
; KUI>LOAD EXAM1
; KUI>ODT ! Use KUI ODT to verify that the destination
; . addresses are cleared
; .
; ODT>^C
; KUI>EXECUTE ! Execute EXAM1
; KUI>ODT ! Use KUI ODT to verify that the transfer was
; . successful
; .
; ODT>^C
; KUI>EXIT
;
; SET UP REGISTER ASSIGNMENTS
MMREG = 174470 ; MASTER MODE REGISTER
CMDREG = 174454 ; COMMAND REGISTER
CASTF0 = 174446 ; CHANNEL 0 CHAIN ADDRESS SEGMENT/TAG FIELD
CAOF0 = 174442 ; CHANNEL 0 CHAIN ADDRESS OFFSET FIELD
START: MOVB #130,MMREG ; LOAD MASTER MODE REG TO DISABLE DTC
CLRB CMDREG ; RESET THE DTC
MOV #0,CASTF0 ; LOAD THE CHAIN ADDRESS REGISTER SEG/TAG
MOV #RELOAD,CAOF0 ; LOAD THE CHAIN ADDRESS REGISTER OFFSET
MOVB #131,MMREG ; LOAD MASTER MODE REG TO ENABLE DTC
MOVB #102,CMDREG ; SET SOFTWARE REQUEST CHANNEL 0
MOVB #240,CMDREG ; START CHAIN CHANNEL 0
BR . ; STAY HERE WHILE THE USER VERIFIES
; THAT THE PROGRAM WAS SUCCESSFUL
; CHAIN LOAD REGION
RELOAD: .WORD 001602 ; RELOAD WORD
